Abstract: A mobile storage device with access control includes a portable storage device and an access control device. The access control device has a non-volatile memory for storing an access-control setting information. If the access-control setting information has already been set with required parameters and when the portable storage device with the access control device is connected to a master equipment, the portable storage device is automatically switched to a secured private zone for the master equipment to access the secured private zone. Further, an agreement to recognize the access-control setting information is made in each time of access if the access control device requires the agreement.

Abstract: An allocation structure is used for a flash memory device. The flash memory device includes a first memory module and a second memory module. The first memory module and the second memory module respectively have a plurality of groups, and each of the groups of the first memory module has a plurality of physical blocks of the first memory module and each of the groups of the second memory module has a plurality of physical blocks of the second memory module. The allocation structure includes a first zone. The first zone is used to store a first allocation unit, and is formed by a first group of the groups of the first memory module and a first part of a second group of the groups of the second memory module.

Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.

Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.

Abstract: A package structure of a memory card includes a substrate. The substrate has connection pads on a first surface and conductive lead structures respectively coupled with the connection pads and extending to a second surface of the substrate. At least one chip is disposed over the substrate at the first surface. A plurality of bonding structures is respectively coupled between the conductive lead structures and the connection pads. A first packaging material layer with a desired thickness is formed on the substrate, wherein the first packaging material layer has an opening region not cover the chip and the bonding structures. A second packaging material layer with the same thickness as that of the first packaging material layer fills the opening region of the first packaging material layer. A packaging method for the memory card is also provided.

Abstract: A memory driving circuit has a register for receiving a new-coming data and a delayed clock, and exporting a current-existing data. The delayed clock has a delay to a clock. A pre-detecting circuit receives the current-existing data, the new-coming data, and a pre-enable signal, and exports an output signal. Wherein, the current-existing data is compared with the new-coming data. The output signal indicates a disable state if the two data are the same. Otherwise, the output signal indicates an enable state, wherein the pre-enable signal is also used to enable or disable the pre-detecting circuit. An output driving circuit receives the current-existing data and an enabling signal, and exports a first output signal. A pre-driving circuit receives the output signal of the pre-detecting circuit and an enable control signal, and exports a second output signal. An I/O pad receives the first output signal and the second output signal.

Abstract: A memory driving circuit has a register for receiving a new-coming data and a delayed clock, and exporting a current-existing data. The delayed clock has a delay to a clock. A pre-detecting circuit receives the current-existing data, the new-coming data, and a pre-enable signal, and exports an output signal. Wherein, the current-existing data is compared with the new-coming data. The output signal indicates a disable state if the two data are the same. Otherwise, the output signal indicates an enable state, wherein the pre-enable signal is also used to enable or disable the pre-detecting circuit. An output driving circuit receives the current-existing data and an enabling signal, and exports a first output signal. A pre-driving circuit receives the output signal of the pre-detecting circuit and an enable control signal, and exports a second output signal. An I/O pad receives the first output signal and the second output signal.

Abstract: A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.

Abstract: The present application discloses methods to provide defect management, wear leveling and data security to a mass storage system implemented using flash memory. The flash memory is organized into a plurality of blocks. Each block has a special region for storing its attributes. In defect management, defects arising from manufacturing and on-the-fly defects are scanned. Defective blocks are marked by altering its attributes. The present application also discloses a wear leveling method in which the difference between the number of erasures of any two blocks (except the defective blocks) is within a predetermined value. The present application further discloses a new error detection and correction method. The same data is stored in two separate memory locations. The content of these two locations are later "ored" or "anded" together (depending on the nature of error giving rise to the error) to recover the correct data.

Abstract: An architecture for a mass storage system using flash memory is described. This architecture involves organizing the flash memory into a plurality of blocks. These blocks are then divided into several categories. One of the categories is a working category used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system). The other category is a temporary buffer used to store data intended to be written to one of the working blocks. Another category contains blocks that need to be erased. When data is written into the mass storage system, a block in the second category is allocated from a block in the third category. The allocated block will then be changed to a block in the first category when writing to the allocated block is completed. The correspond block in the first category is placed into the third category. As a result, blocks can be recycled.

Abstract: An architecture for a mass storage system using flash memory is described. This architecture involves organizing the flash memory into a plurality of blocks. These blocks are then divided into several categories. One of the categories is a working category used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system). The other category is a temporary buffer used to store data intended to be written to one of the working blocks. Another category contains blocks that need to be erased. When data is written into the mass storage system, a block in the second category is allocated from a block in the third category. The allocated block will then be changed to a block in the first category when writing to the allocated block is completed. The correspond block in the first category is placed into the third category. As a result, blocks can be recycled.

Abstract: A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.