Patents by Inventor Ting-En HSIEH
Ting-En HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Patent number: 11929407Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.Type: GrantFiled: May 30, 2022Date of Patent: March 12, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Publication number: 20230261083Abstract: A method of manufacturing a semiconductor device includes providing a substrate. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A source and a drain are formed on the barrier layer. A recess is formed in the barrier layer, in which the recess has a bottom surface, and a portion of the barrier underneath the recess has a thickness. A first dielectric layer is formed to cover the bottom surface of the recess. A charge trapping layer is formed on the first dielectric layer. A first ferroelectric material layer is formed on the charge trapping layer. A second dielectric layer is formed on the first ferroelectric material layer. A second ferroelectric material layer is formed on the second dielectric layer. A gate is formed over the second ferroelectric material layer.Type: ApplicationFiled: April 20, 2023Publication date: August 17, 2023Inventors: Edward Yi CHANG, Shih-Chien LIU, Chung-Kai HUANG, Chia-Hsun WU, Ping-Cheng HAN, Yueh-Chin LIN, Ting-En HSIEH
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Patent number: 11670699Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.Type: GrantFiled: March 4, 2020Date of Patent: June 6, 2023Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Edward Yi Chang, Shih-Chien Liu, Chung-Kai Huang, Chia-Hsun Wu, Ping-Cheng Han, Yueh-Chin Lin, Ting-En Hsieh
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Publication number: 20220293747Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.Type: ApplicationFiled: May 30, 2022Publication date: September 15, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Patent number: 11380767Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.Type: GrantFiled: April 28, 2020Date of Patent: July 5, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Publication number: 20220148938Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: ApplicationFiled: November 9, 2020Publication date: May 12, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Shin-Cheng LIN, Cheng-Wei CHOU, Ting-En HSIEH, Yi-Han HUANG, Kwang-Ming LIN, Yung-Fong LIN, Cheng-Tao CHOU, Chi-Fu LEE, Chia-Lin CHEN, Shu-Wen CHANG
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Publication number: 20210336016Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Inventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Publication number: 20200203499Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.Type: ApplicationFiled: March 4, 2020Publication date: June 25, 2020Inventors: Edward Yi CHANG, Shih-Chien LIU, Chung-Kai HUANG, Chia-Hsun WU, Ping-Cheng HAN, Yueh-Chin LIN, Ting-En HSIEH
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Publication number: 20180175185Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material.Type: ApplicationFiled: July 10, 2017Publication date: June 21, 2018Inventors: Edward Yi CHANG, Shih-Chien LIU, Chung-Kai HUANG, Chia-Hsun WU, Ping-Cheng HAN, Yueh-Chin LIN, Ting-En HSIEH
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Publication number: 20160133738Abstract: A high electron mobility transistor is realized in the present invention by a gate recessed structure, a high permittivity oxide layer and a nitride-based interfacial passivation layer, featuring high threshold voltage, high transconductance, highly stable drain output current, and high reliability.Type: ApplicationFiled: January 14, 2015Publication date: May 12, 2016Inventors: Edward Yi CHANG, Yueh-Chin LIN, Ting-En HSIEH