Abstract: The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal.

Abstract: A communication device and receiving method thereof are disclosed in embodiments of the present invention. The communication device includes an extra digital to analog converter, an inverse partial response filtering circuit and an analog to digital converter. The extra digital to analog converter receives a first digital signal and generates a pulse shaped analog signal. The inverse partial response filtering circuit receives a first difference signal, and adjusts a response of the inverse partial response filtering circuit to generate an adjusted signal, wherein the first difference signal equals the result of subtracting the pulse shaped analog signal from a receiving signal. The analog to digital converter converts the adjusted signal to generate a second digital signal.

Abstract: A communication device and the method thereof are disclosed in embodiments of the present invention. The communication device includes a level determining module, an digital to analog converter and an analog to digital converter. The level determining module determines a plurality of voltage levels and voltage intensity thereof according to an estimating signal to generate a first digital signal. The digital to analog converter converts the first digital signal into a pulse shaped analog signal according to the plurality of voltage levels and voltage intensity thereof. The analog to digital converter converts a first difference signal into a second digital signal wherein the first difference signal equals the result of subtracting the pulse shaped analog signal from a receiving signal.

Abstract: A frequency-phase adjusting device includes a first controller, a second controller, and an oscillating circuit. The first controller generates a first control signal according to a target frequency and a current frequency. The second controller generates a second control signal according to the first control signal, wherein the second control signal is related to a first frequency difference, a second frequency difference, and a designated duration. The oscillating circuit adjusts the current frequency according to the first frequency difference, the second frequency difference, and the designated duration. The current frequency is set as a first frequency during a first duration, set as a second frequency during the designated duration, and set as a third frequency during a second duration. The first frequency difference equals a difference between the first frequency and the second frequency, and the second frequency difference equals a difference between the second frequency and the third frequency.

Abstract: A communication system includes a first network device and a second network device. A power consumption control method applied to the communication system includes the steps of: checking a receiving capability of the first network device to generate a first checking result; and selectively notifying the second network device to adjust a transmitting capability of the second network device according to the first checking result. When the first checking result indicates that the receiving capability of the first network device is greater than a first threshold, transmit a first notice signal to notify the second network device. When receiving the first notice signal, lower the transmitting capability of the second network device.

Abstract: The present invention discloses a network interface apparatus comprising two power regulators, one of which is a system power regulator for supplying a first supply voltage to a physical layer and a medium access control layer in the network interface apparatus, and the other one is an uninterrupted power regulator for supplying a second supply voltage to a power management module. When the network interface apparatus operates in a disconnection status, the system power regulator is disabled so as not to supply the first supply voltage, and the uninterrupted power regulator still provides the second supply voltage to the power management module.

Abstract: An echo signal processing apparatus is disclosed. The echo signal processing apparatus is utilized for generating a cancellation signal by using group phenomenon of a frequency response of an echo signal to remove the echo signal. The echo signal processing apparatus has lower cost and is able to remove the echo efficiently.

Abstract: A communication apparatus with echo cancellation includes a transmitter, a receiver, a digital echo cancellation circuit, a parameter control circuit, and an analog echo cancellation circuit. The digital echo cancellation circuit determines an echo estimation component according to a digital output signal, and performs a digital echo cancellation on a digital input signal according to the echo estimation component. The parameter control circuit generates a control signal according to the echo estimation component. The analog echo cancellation circuit includes a first echo cancellation resistor and a second echo cancellation resistor, wherein the resistances of the first echo cancellation resistor and the second echo cancellation resistor are adjusted according to the control signal.

Abstract: A network signal processing apparatus includes: a transceiver for transmitting or receiving a network signal, and a transformer coupled to the transceiver and a network connecting port for transmitting or receiving the network signal. The transformer includes: a first coil, which is coupled to the transceiver and has a first turn number; and a second coil, which is coupled to the network connecting port and has a second turn number. The second turn number is different from the first turn number.

Abstract: A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock.

Abstract: A wired network connection establishing method includes the steps of: configuring two network devices to exchange connection capacity information with each other through first and second twisted pair cables of a network cable, the connection capacity information including at least a first connection mode using four of the twisted pair cables, a second connection mode using three of the twisted pair cables, and a third connection mode using two of the twisted pair cables; configuring the two network devices to detect a number of the twisted pair cables in the network cable capable of supporting a normal connection; and configuring the two network devices to determine which one of the first, second, and third connection modes is to be used for establishing a connection based on the number of the twisted pair cables capable of supporting a normal connection.

Abstract: A transceiver in a communication system and a start-up method thereof are provided. The transceiver comprises an auto-negotiation circuit, a timing recovery circuit, an interference cancellation circuit and an equalizer. The auto-negotiation circuit performs an auto-negotiation procedure to determine whether the transceiver operates as a master or slave transceiver. If the transceiver operates as a slave transceiver, it executes a first stage and a second stage during the start-up process. In the first stage, the transceiver performs channel estimation to generate a channel estimation value, presets the parameters of the equalizer according to the channel estimation value, and trains the timing recovery circuit and the equalizer; in the second stage, the transceiver trains the interference cancellation circuit.

Abstract: A power-saving network apparatus includes a MAC and a PHY. The PHY includes a transmitter and a receiver. The transmitter executes the operations of: transmitting a data signal to a remote network apparatus according to output packets of the MAC when the transmitter enters a normal state; transmitting an idle signal to the remote network apparatus when the transmitter enters an idle state; transmitting an indication signal to the remote network apparatus to notify it to enter a low power state, wherein the indication signal is different from the idle signal; entering the idle state or the normal state from the low power state in response to at least one of a predetermined period and a transmitting enable signal.

Abstract: A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.