Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: Mapping information management for data storage devices is provided. A controller caches write data issued by a host in a temporary storage and then programs the cached write data from the temporary storage to a non-volatile memory. The controller uses a mapping information format to manage mapping information of logical addresses recognized by the host. As presented in the mapping information format, the values not greater than a first threshold value and mapped to the configuration information storage space of the non-volatile memory are at least partially used to point to the temporary storage, and the values greater than the first threshold value are mapped to the non-volatile memory.

Abstract: Mapping information management for data storage. A mapping information format without any uncorrectable flag bits (UNC bits) is shown. A controller provides a cyclic redundancy check (CRC) engine. In response to an uncorrectable marking command issued by a host, the controller operates the cyclic redundancy check engine to encode a data pattern with a biased encoding seed to generate biased cyclic redundancy check code. The controller programs the data pattern and the biased cyclic redundancy check code to the non-volatile memory. The data pattern, therefore, will not pass CRC. The uncorrectable marking command works.

Abstract: High-efficiency control technology for non-volatile memory is shown. A controller allocates spare blocks of a non-volatile memory to provide a first active block and writes data issued by a host to the first active block. When the number of spare blocks is less than a threshold number and valid data of a first source block is less than a critical data amount, the controller uses the first active block as a data transfer destination for the valid data from the first source block.

Abstract: High-efficiency control technology for non-volatile memory is shown. A controller transfers valid data from a first source block to an active block in sections and, between segmented data transfers, the controller writes data issued by the host to the active block. When no second source block is waiting, the controller transfers a first amount of valid data from the first source block to the active block in each segmented data transfer. When a second source block is waiting, the controller transfers a second amount of valid data from the first source block to the active block in each segmented data transfer. The second amount is larger than the first amount and thereby the data transfer for the first source block speeds up.

Abstract: High-efficiency control technology for non-volatile memory. A controller allocates spare blocks of a non-volatile memory to provide an active block and writes data issued by a host to the active block. The controller further uses the active block as the destination for data transferred from a first source block when there are fewer spare blocks than the threshold amount. When a second source block meets the transfer requirements, the controller uses the active block as the destination for data transferred from the second source block.

Abstract: Mapping information management for data storage devices is provided. A controller caches write data issued by a host in a temporary storage and then programs the cached write data from the temporary storage to a non-volatile memory. The controller uses a mapping information format to manage mapping information of logical addresses recognized by the host. As presented in the mapping information format, the values not greater than a first threshold value and mapped to the configuration information storage space of the non-volatile memory are at least partially used to point to the temporary storage, and the values greater than the first threshold value are mapped to the non-volatile memory.

Abstract: Mapping information management for data storage. A mapping information format without any uncorrectable flag bits (UNC bits) is shown. A controller provides a cyclic redundancy check (CRC) engine. In response to an uncorrectable marking command issued by a host, the controller operates the cyclic redundancy check engine to encode a data pattern with a biased encoding seed to generate biased cyclic redundancy check code. The controller programs the data pattern and the biased cyclic redundancy check code to the non-volatile memory. The data pattern, therefore, will not pass CRC. The uncorrectable marking command works.

Abstract: High-efficiency control technology for non-volatile memory. A controller allocates spare blocks of a non-volatile memory to provide an active block and writes data issued by a host to the active block. The controller further uses the active block as the destination for data transferred from a first source block when there are fewer spare blocks than the threshold amount. When a second source block meets the transfer requirements, the controller uses the active block as the destination for data transferred from the second source block.

Abstract: High-efficiency control technology for non-volatile memory is shown. A controller allocates spare blocks of a non-volatile memory to provide a first active block and writes data issued by a host to the first active block. When the number of spare blocks is less than a threshold number and valid data of a first source block is less than a critical data amount, the controller uses the first active block as a data transfer destination for the valid data from the first source block.

Abstract: High-efficiency control technology for non-volatile memory is shown. A controller transfers valid data from a first source block to an active block in sections and, between segmented data transfers, the controller writes data issued by the host to the active block. When no second source block is waiting, the controller transfers a first amount of valid data from the first source block to the active block in each segmented data transfer. When a second source block is waiting, the controller transfers a second amount of valid data from the first source block to the active block in each segmented data transfer. The second amount is larger than the first amount and thereby the data transfer for the first source block speeds up.

Abstract: A notebook computer including a bottom case and a top panel is provided, wherein the top panel includes a first supporting element, a top panel body and a second supporting element. The first supporting element has a first side and a second side, wherein the first side pivots to the bottom case, and the top panel body pivots to the first side of the first supporting element. The top panel body has multiple sets of first fixing structure. The second supporting element has a third side and a fourth side, wherein the third side pivots to the second side of the first supporting element. The fourth side has a set of second fixing structures, which is inserted into one set of the first fixing structures.

Abstract: A notebook computer including a bottom case and a top panel is provided, wherein the top panel includes a first supporting element, a top panel body and a second supporting element. The first supporting element has a first side and a second side, wherein the first side pivots to the bottom case, and the top panel body pivots to the first side of the first supporting element. The top panel body has multiple sets of first fixing structure. The second supporting element has a third side and a fourth side, wherein the third side pivots to the second side of the first supporting element. The fourth side has a set of second fixing structures, which is inserted into one set of the first fixing structures.