Patents by Inventor Ting-Han Su

Ting-Han Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160077986
    Abstract: The present disclosure provides an electronic apparatus that comprises a number of Universal Serial Bus (USB) device control modules, a microprocessor, a priority arbitration module, a USB host control module and a USB hub module. The USB device control modules are configured to receive from and send to a host a USB electric signal. The microprocessor is configured to generate a number of virtual USB hub modules in a memory. Each of the virtual USB hub modules is configured to generate a USB device enumeration signal, in response to an electric connection status between a USB electronic device and the USB hub module, and to send the USB device enumeration signal via a corresponding one of the USB device control modules to the host. The priority arbitration module is configured to, in response to the availability of the USB electronic device, transmit the USB electric signal issued from the host to the USB electronic device via the USB host control module and the USB hub module.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 17, 2016
    Inventors: JACK WANG, YUNG-CHI CHUNG, TSUNG MING SHEN, TING-HAN SU
  • Patent number: 7886141
    Abstract: This invention relates to an advanced system and method of reprogrammable boot codes and In Application Programming (IAP) of embedded systems by booting up with boot loader to shadow program codes on to an internal high speed SRAM and extending contiguously to external higher space memory for runtime applications, and supporting on-line IAP to update run-time firmware or boot loader driver through network communication by utilizing advanced address remapping scheme as well as supporting In System Programming (ISP) to program initial Flash memory via ISP adaptor.
    Type: Grant
    Filed: October 27, 2007
    Date of Patent: February 8, 2011
    Assignee: Asix Electronics Corporation
    Inventors: Hsun-Yao Jan, Ting-Han Su
  • Patent number: 7673200
    Abstract: The present invention discloses a reprogrammable built-in-self-test integrated circuit and a test method for the same, wherein test programs are directly stored in the application program memory of the logic chip of a SoC IC, and an external test apparatus is used to load the test programs into the application program memory via a serial transmission interface, and an application CPU is used to read and execute the test programs to perform the bonding-wire connectivity between the logic chip and the memory chip. In the present invention, test vectors can still be flexibly revised after tapeout to increase test coverage. As the test programs are directly stored in the existing application program memory without using additional memory space, and as the test programs are executed by the existing application CPU without using an extra built-in-self-test circuit, the present invention can effectively reduce test cost.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: March 2, 2010
    Assignee: Asix Electronics Corporation
    Inventors: Hsun-Yao Jan, Ting-Han Su, Cheng-Fang Yang
  • Publication number: 20090113196
    Abstract: This invention relates to an advanced system and method of reprogrammable boot codes and In Application Programming (IAP) of embedded systems by booting up with boot loader to shadow program codes on to an internal high speed SRAM and extending contiguously to external higher space memory for runtime applications, and supporting on-line IAP to update run-time firmware or boot loader driver through network communication by utilizing advanced address remapping scheme as well as supporting In System Programming (ISP) to program initial Flash memory via ISP adaptor.
    Type: Application
    Filed: October 27, 2007
    Publication date: April 30, 2009
    Inventors: Hsun-Yao JAN, Ting-Han Su
  • Publication number: 20090100305
    Abstract: The present invention discloses a reprogrammable built-in-self-test integrated circuit and a test method for the same, wherein test programs are directly stored in the application program memory of the logic chip of a SoC IC, and an external test apparatus is used to load the test programs into the application program memory via a serial transmission interface, and an application CPU is used to read and execute the test programs to perform the bonding-wire connectivity between the logic chip and the memory chip. In the present invention, test vectors can still be flexibly revised after tapeout to increase test coverage. As the test programs are directly stored in the existing application program memory without using additional memory space, and as the test programs are executed by the existing application CPU without using an extra built-in-self-test circuit, the present invention can effectively reduce test cost.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 16, 2009
    Inventors: Hsun-Yao Jan, Ting-Han Su, Cheng-Fang Yang