Patents by Inventor Ting HAO

Ting HAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973511
    Abstract: An analog-to-digital converting device includes N-stage first analog-to-digital converters (ADCs), a second ADC, a first calibration circuit, a data recovery circuit and an output circuit. The N-stage first ADCs has a first sampling frequency that is (N+1)/N times of a second sampling frequency, and converts an input signal into first quantized outputs. The second ADC has the second sampling frequency, and converts the input signal into a second quantized output. The first calibration circuit calibrates offsets of the first quantized outputs and the second quantized output to generate third quantized outputs and a fourth quantized output. The data recovery circuit outputs, by the second sampling frequency, one of the third quantized outputs as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate output data. The output circuit generates an output signal according to the third quantized outputs and the output data.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: April 30, 2024
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Hao Wang, Hsin-Han Han
  • Patent number: 11968817
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11956167
    Abstract: Provided are a channel configuration method and terminal, a storage medium and an electronic device. The method includes: determining that multiple physical channels overlap in a time domain; and determining a physical channel for carrying information or data in the multiple physical channels, wherein the determined physical channel is a Physical Uplink Control Channel (PUCCH), and determining a physical channel comprises: among the multiple physical channels, processing a physical channel with earlier first symbol before a physical channel with later first symbol, and when two or more physical channels in the multiple physical channels have the same first symbol, processing a physical channel with a larger number of symbols before a physical channel with a smaller number of symbols.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: April 9, 2024
    Assignee: ZTE Corporation
    Inventors: Wei Gou, Peng Hao, Zhisong Zuo, Ting Fu
  • Patent number: 11955423
    Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
  • Patent number: 11951120
    Abstract: This invention relates to the fields of mRNA vaccines, mRNA therapy, and gene therapy and specifically to the use of gene expression vectors or PCR amplicons containing various 5?UTR sequences followed by coding sequences for in vitro and in vivo production of mRNA or proteins of interest.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: April 9, 2024
    Inventors: Jaewoo Lee, Dehua Wang, Xiaoyao Hao, Yue Gao, Jie Liu, Shan He, Ting He, Dan Tse
  • Publication number: 20240112924
    Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Hsu-Hsien Chen, Chen-Shien Chen, Ting Hao Kuo, Chi-Yen Lin, Yu-Chih Huang
  • Publication number: 20240106757
    Abstract: A method of wireless signal transmission management includes transmitting a plurality of data packets to tethering equipment from user equipment to tethering equipment, determining a size of each of the plurality of data packets by the tethering equipment, designating data packets of the plurality of data packets having a specific range of sizes as control signal packets by the tethering equipment, and prioritizing in transmitting the control signal packets to a cellular network by the tethering equipment.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 28, 2024
    Applicant: MEDIATEK INC.
    Inventors: Ching-Hao Lee, Yi-Lun Chen, Ho-Wen Pu, Yu-Yu Hung, Jun-Yi Li, Ting-Sheng Lo
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Publication number: 20240096827
    Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Chen-Shien Chen, Ting-Li Yang, Po-Hao Tsai, Chien-Chen Li, Ming-Da Cheng
  • Publication number: 20240082382
    Abstract: The present invention relates to a human papillomavirus type 31 chimeric protein and a use thereof. Specifically, the present invention relates to a human papillomavirus chimeric protein, containing or being composed of an HPV31L1 protein or HPV31L1 protein mutant, and a polypeptide derived from an HPV73L2 protein and inserted into the HPV31L1 protein or HPV31L1 protein mutant, wherein the HPV31L1 protein is as shown in SEQ ID No. 1, and the HPV73L2 protein is as shown in SEQ ID No. 2.
    Type: Application
    Filed: September 26, 2021
    Publication date: March 14, 2024
    Inventors: Xuemei Xu, Yaru Hao, Ting Zhang, Mingrao Ma
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11926909
    Abstract: To provide a gas-liquid separator of a water electrolysis system, comprising: a liquid feeding atomizer and a gas-liquid separation chamber, wherein the liquid feeding atomizer includes a liquid feeding pressurized tube; and an atomizing spray head, in which the atomizing spray head converts a gas-liquid mixed liquor after pressurized by the liquid feeding pressurized tube into a mist droplet gas-liquid mixture. The gas-liquid separation chamber comprises a spiral flowing way, and the spiral flowing way extends the time that the mist droplet gas-liquid mixture spraying into the gas-liquid separation chamber flows downwards to the bottom of the gas-liquid separation chamber; an ultrasonic oscillation mechanism; a stirrer; an internal reservoir; and a filter mechanism, which performs the gas-liquid separation for unbroken bubbles in the mist droplet gas-liquid mixture through the pore difference.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: March 12, 2024
    Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chia-Kan Hao, Kuan-Ting Lai, Chung-Yen Lu
  • Patent number: 11924682
    Abstract: Provided are a response receiving and sending method, a retransmission method, a communication device, and a storage medium. The method includes: sending a transport block to a first communication device through a pre-configured period resource, and receiving a correct response corresponding to the transport block on a pre-configured correct response resource.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 5, 2024
    Assignee: ZTE CORPORATION
    Inventors: Shuqiang Xia, Ting Fu, Peng Hao, Chunli Liang, Min Ren, Wei Gou, Jing Shi, Xianghui Han
  • Publication number: 20240071833
    Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Huan Chen, Huan-Chih Yuan, Yu-Chang Jong, Scott Yeh, Fei-Yun Chen, Yi-Hao Chen, Ting-Wei Chou
  • Publication number: 20240074027
    Abstract: A capacitor capable of releasing reactive oxygen species and reactive nitrogen species after powering of claim 1 is composed of the dielectric material. A plurality of through holes are designed on the capacitor, the through holes being used as air gaps to supply plasma gas and blow a fan to increase the gas flow, and the voltage being connected to the two corresponding electrode edges of the capacitor so that the capacitor generating a heating temperature (lower than 200 degrees Celsius). Thereby, after the capacitor is perforated to form honeycomb shape and powered, the air surrounding the capacitor flowing through the capacitor is ionized to the oxygen ion and nitrogen ion via heating and charge-discharge, generates plasma at room temperature and atmospheric pressure and releases the reactive oxygen ions and reactive nitrogen ions healing and helpful for body healing.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Chung-Tai Chang, Chia-Hao Chang, Ting-Yi Chang
  • Publication number: 20240072816
    Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.
    Type: Application
    Filed: November 21, 2022
    Publication date: February 29, 2024
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hao Wang, Hui-Wen Tsai, Shih-Chun Lo
  • Patent number: 11913925
    Abstract: A sensing device is provided. The sensing device includes a processing circuit and a multi-sensor integrated single chip. The multi-sensor integrated single chip includes a substrate and a temperature sensor, a pressure sensor, and an environmental sensor disposed on the substrate. The temperature sensor senses temperature. The pressure sensor senses pressure. The environmental sensor senses an environmental state. The processing circuit obtains a first sensed temperature value from the temperature sensor when the environmental sensor does not operate, and it obtains a second sensed temperature value from the temperature sensor when the environmental sensor operates. The processing circuit obtains a sensed pressure value from the pressure sensor. The processing circuit obtains at least one temperature calibration reference of the pressure sensor according to the first and second sensed temperature values and calibrates the sensed pressure value according to the temperature calibration reference.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ying-Che Lo, Yu-Sheng Lin, Po-Jen Su, Ting-Hao Hsiao
  • Publication number: 20240053676
    Abstract: A method includes performing a lithography process using a mask and a pellicle membrane; detaching the pellicle membrane from the mask after the lithography process is completed; performing an inspection process to the pellicle membrane, the inspection process including generating a laser beam toward the pellicle membrane from a laser source, such that the laser beam passes through the pellicle membrane; and generating an image by receiving the laser beam passing through the pellicle membrane using an image sensor; and determining whether a particle is present on the pellicle membrane or a pin hole is present in the pellicle membrane based on the image.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Hao CHANG, Pei-Cheng HSU, Chih-Cheng CHEN, Huan-Ling LEE, Ting-Hao HSU, Hsin-Chang LEE
  • Patent number: 11876945
    Abstract: A method for acquiring shadow-free images of a document for scanning or other purposes is applied in a device. The method includes training a shadow prediction model based on sample documents of a sample library and inputting a background color and a shadow mask of each of the sample documents extracted by the shadow prediction model into a predetermined shadow removing network for training, to obtain a shadow removing model. The method further includes obtaining a background color and a shadow mask of the document through the shadow prediction model and removing the shadows of the document based on the shadow removing model. The device utilizing the method is also disclosed.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 16, 2024
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Yun-Hsuan Lin, Yung-Yu Chuang, Nai-Sheng Syu, Tzu-Kuei Huang, Ting-Hao Chung, Yu-Ching Wang, Chun-Hsiang Huang
  • Patent number: 11855099
    Abstract: A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: December 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Ting-Hao Hsu