Abstract: A system having a Reconfigurable ReflectArray (RRA) structure includes a radiation layer and a control layer. The radiation layer includes at least one P-Intrinsic-N (P-I-N) diode and a plurality of reconfigurable reflective units. At least one part of the reconfigurable reflective units is electrically connected to the at least one P-I-N diode. The control layer includes at least one switch element and at least one control unit. The at least one switch element is electrically connected to the radiation layer. The at least one control unit is electrically connected to the at least one switch element. The number of the reconfigurable reflective units is different from the number of the at least one switch element.

Abstract: A method includes forming a dummy component, including: forming through-substrate vias (TSVs) in a substrate; forming a thermal structure over the TSVs, wherein the thermal structure includes metal lines in dielectric layers; forming a bonding layer over the thermal structure; and forming bond pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A first lower semiconductor device and a second lower semiconductor device are provided. A plurality of first conductive pillars are formed on the first lower semiconductor device along a first direction parallel to a side of the first lower semiconductor device. A plurality of second conductive pillars are formed on the second lower semiconductor device along a second direction parallel to a side of the second lower semiconductor device, wherein the first direction is substantially collinear with the second direction. An upper semiconductor device is disposed on the first lower semiconductor device and the second lower semiconductor device and revealing a portion where the plurality of first conductive pillars and the plurality of second conductive pillars are disposed.

Abstract: A device includes a package component including an interconnect structure on a first side of a substrate; metal pads on the interconnect structure; a semiconductor die connected to a second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer over the passivation layer, wherein the first buffer layer extends over the package component and over the dielectric material, wherein a width of the first buffer layer is greater than a width of the package component and is less than a width of the passivation layer; and conductive connectors penetrating the passivation layer and the first buffer layer to physically contact the metal pads.

Abstract: An anti-warpage reinforced carrier includes a substrate, a plurality of rigid insulating plates, a plurality of metal posts, a resin layer, a first circuit layer, and a second circuit layer. The rigid insulating plates are arranged on the positioning areas on the substrate. The metal posts are in the second through holes penetrating through the rigid insulating plate. The resin layer covers the rigid insulating plates and the upper surface of the substrate, and includes a plurality of openings. The first circuit layer is on the resin layer and in the openings, and is connected to the metal posts. The second circuit layer is on a lower surface of the substrate and in the first through holes penetrating through the substrate, and is connected to the metal posts. By embedding rigid insulating plates therein, the anti-warpage reinforced carrier provides thermal stability, and is suitable for applications in advanced chip packaging.

Abstract: A composite package includes a first semiconductor die which includes a semiconductor substrate; dielectric material layers overlying the semiconductor substrate; an edge ring seal structure laterally enclosing the dielectric material layers without any lateral opening therethrough; at least one passivation dielectric layer overlying the dielectric material layers; and a capping metal ring contacting a top surface segment of the edge ring seal structure and laterally surrounding a lower portion of the at least one passivation dielectric layer. Each corner region of the at least one passivation dielectric layer is free of any metallic material other than a respective single slanted bar segment of the capping metal ring. Alternatively or additionally, a spacer metal ring having a different height than the capping metal ring may be formed within the at least one passivation dielectric layer.

Abstract: A Reconfigurable ReflectArray (RRA) structure includes a P-Intrinsic-N (P-I-N) diode and a metal circuit. The metal circuit includes a first metal member and a second metal member. The first metal member is coupled to one end of the P-I-N diode. The second metal member is coupled to another end of the P-I-N diode. One of the first metal member and the second metal member includes a first radiating portion and a second radiating portion. The first radiating portion is located between the P-I-N diode and the second radiating portion. The first radiating portion has a first length. The second radiating portion has a second length. The first length is different from the second length.

Abstract: A method for estimating performance values of chips includes: (A) using oscillation period vectors of a to-be-divide chip set to train a first neural network model to obtain a training error of the to-be-divided chip set, where in the first-time conducted step (A), the to-be-divided chip set includes the chips; (B) dividing the to-be-divided chip set into divided chip sets according to the training error; and (C) using oscillation period vectors of the divided chip sets as training data of a second neural network model, so that the second neural network model outputs weight vectors respectively corresponding to the divided chip sets. A product of oscillation period vector(s) of each divided chip set and a weight vector of the divided chip set is larger than a product of the oscillation period vector(s) of the divided chip set and a weight vector of each of rest of divided chip sets.

Abstract: Gap-fill dielectrics for die structures and methods of forming the same are provided. In an embodiment, a device includes: an outer gap-fill dielectric having a first coefficient of thermal expansion; a first integrated circuit die in the outer gap-fill dielectric; a second integrated circuit die in the outer gap-fill dielectric; an inner gap-fill dielectric between the first integrated circuit die and the second integrated circuit die, the inner gap-fill dielectric having a second coefficient of thermal expansion, the second coefficient of thermal expansion being greater than the first coefficient of thermal expansion; and a third integrated circuit die over the inner gap-fill dielectric, the third integrated circuit die bonded to the first integrated circuit die and to the second integrated circuit die.

Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.

Abstract: A semiconductor die includes lower dies separated by a dielectric region; a cross die vertically stacked on the lower dies and the dielectric region; a molding structure filling the dielectric region and surrounding side surfaces of the lower dies and the cross die; and a bonding ring connecting the cross die to the lower dies and including: an upper metal ring formed in a bottom surface of the cross die; and a lower metal ring formed in top surfaces of the lower dies and extending through the molding structure in the dielectric region. The lower metal ring is bonded to the upper metal ring.

Abstract: A method of scanning a substrate and determining scratches of the substrate includes transmitting a converging beam of light that comprises multiple wavelengths to the substrate. Each wavelength of the multiple wavelengths focuses at a different distance in a focus interval around and including a surface of the substrate. The method also includes receiving reflected light from the surface of the substrate and determining a height or depth of the surface of the substrate based on a wavelength of the reflected light having a highest intensity.

Abstract: A semiconductor structure comprises: a semiconductor substrate; one or more first implant layers disposed in the semiconductor substrate and forming a circuit portion and a first test portion, the circuit portion forming an at least partially formed semiconductor circuit; and one or more second implant layers disposed in the semiconductor substrate and further forming the circuit portion and a second test portion, wherein the first and second test portions are spaced apart. A first implantation profile of the one or more first implant layers of the first test portion is obtained during a testing procedure, and the first implantation profile is a representation of a second implantation profile of the one or more first implant layers of the circuit portion.

Abstract: A calibration system includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit and a first calculation circuit. The jitter-capturing ADC is configured to sample a to-be-sampled clock signal according to an operating clock signal to generate a first quantized output. The calibration value generating circuit is configured to receive the first quantized output and a second quantized output of a to-be-calibrated ADC to generate a calibration value. The operating clock signal is for driving the to-be-calibrated ADC to sample, and the calibration value is related to a phase noise of the operating clock signal. The first calculation circuit is coupled with the calibration value generating circuit, and configured to subtract the calibration value from the second quantized output to generate a third quantized output.

Abstract: A method of scanning a substrate and determining scratches of the substrate includes transmitting a converging beam of light that comprises multiple wavelengths to the substrate. Each wavelength of the multiple wavelengths focuses at a different distance in a focus interval around and including a surface of the substrate. The method also includes receiving reflected light from the surface of the substrate and determining a height or depth of the surface of the substrate based on a wavelength of the reflected light a highest intensity.

Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: A temperature sensing device and a calibration method of the temperature sensing device are provided. Based on different conditions, the temperature sensing device generates a first digital sensing value and a second digital sensing value corresponding to an ambient temperature. The temperature sensing device generates a first sensing result value according to the first digital sensing value, a first compensation value, and a sensing difference value between the first digital sensing value and the second digital sensing value, and generates a second sensing result value according to the second digital sensing value, a second compensation value, and the sensing difference value. The temperature sensing device obtains an error from the first sensing result value and the second sensing result value according to a first reference value and a second reference value. The temperature sensing device calibrates the first compensation value according to the error.

Abstract: A device includes: a first integrated circuit (IC) die; a first dielectric material around first sidewalls of the first IC die; a second IC die over and electrically coupled to the first IC die; and a second dielectric material over the first dielectric material and around second sidewalls of the second IC die, where in a top view, the second sidewalls of the second IC die are disposed within, and are spaced apart from, the first sidewalls of the first IC die.

Abstract: A method of inspecting an outer surface of a mask pod includes moving a stage holding a mask pod such that the stage stops at each location of a plurality of locations under an outer surface of the mask pod for a predefined amount of time. At each location of the plurality of locations, the method further includes directing a stream of air to the outer surface of the mask pod, capturing an image of scattered air from each location of the plurality of locations of the outer surface of the mask pod, and determining a number of particles in the scattered air as a sampled number of particles based on the captured image. The method also includes generating a map of particles on the outer surface of the mask pod based on the sampled number of particles at each of the plurality of locations.

Abstract: A network system for identifying a cable connection is provided. The network system includes a management server, a server device, and a storage device. The management server includes system-management software. The server device is connected to the management server. The server device includes a BMC configured to communicate with the system-management software of the management server. The storage device includes at least one cable port configured to receive a storage cable that connects the storage device to the server device. The cable port includes a non-volatile memory, an indicator light, and a I2C bus.