Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.

Abstract: A method includes forming a wafer, and etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer. A first portion of a second dielectric layer of the wafer is directly underlying the first trench. A laser grooving process is then performed to remove the first portion of the second dielectric layer of the wafer and to form a second trench, which is underlying and joined to the first trench. The second dielectric layer includes a corner region where the first trench is joined to the second trench. Portions of a top surface of the corner region closer to a center middle line of the second trench are increasing lower than respective portions of the top surface of the corner region farther away from the center middle line.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: A method includes forming a dummy component, including: forming through-substrate vias (TSVs) in a substrate; forming a thermal structure over the TSVs, wherein the thermal structure includes metal lines in dielectric layers; forming a bonding layer over the thermal structure; and forming bond pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A first lower semiconductor device and a second lower semiconductor device are provided. A plurality of first conductive pillars are formed on the first lower semiconductor device along a first direction parallel to a side of the first lower semiconductor device. A plurality of second conductive pillars are formed on the second lower semiconductor device along a second direction parallel to a side of the second lower semiconductor device, wherein the first direction is substantially collinear with the second direction. An upper semiconductor device is disposed on the first lower semiconductor device and the second lower semiconductor device and revealing a portion where the plurality of first conductive pillars and the plurality of second conductive pillars are disposed.

Abstract: A device includes a package component including an interconnect structure on a first side of a substrate; metal pads on the interconnect structure; a semiconductor die connected to a second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer over the passivation layer, wherein the first buffer layer extends over the package component and over the dielectric material, wherein a width of the first buffer layer is greater than a width of the package component and is less than a width of the passivation layer; and conductive connectors penetrating the passivation layer and the first buffer layer to physically contact the metal pads.

Abstract: A composite package includes a first semiconductor die which includes a semiconductor substrate; dielectric material layers overlying the semiconductor substrate; an edge ring seal structure laterally enclosing the dielectric material layers without any lateral opening therethrough; at least one passivation dielectric layer overlying the dielectric material layers; and a capping metal ring contacting a top surface segment of the edge ring seal structure and laterally surrounding a lower portion of the at least one passivation dielectric layer. Each corner region of the at least one passivation dielectric layer is free of any metallic material other than a respective single slanted bar segment of the capping metal ring. Alternatively or additionally, a spacer metal ring having a different height than the capping metal ring may be formed within the at least one passivation dielectric layer.

Abstract: Gap-fill dielectrics for die structures and methods of forming the same are provided. In an embodiment, a device includes: an outer gap-fill dielectric having a first coefficient of thermal expansion; a first integrated circuit die in the outer gap-fill dielectric; a second integrated circuit die in the outer gap-fill dielectric; an inner gap-fill dielectric between the first integrated circuit die and the second integrated circuit die, the inner gap-fill dielectric having a second coefficient of thermal expansion, the second coefficient of thermal expansion being greater than the first coefficient of thermal expansion; and a third integrated circuit die over the inner gap-fill dielectric, the third integrated circuit die bonded to the first integrated circuit die and to the second integrated circuit die.

Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.

Abstract: A semiconductor die includes lower dies separated by a dielectric region; a cross die vertically stacked on the lower dies and the dielectric region; a molding structure filling the dielectric region and surrounding side surfaces of the lower dies and the cross die; and a bonding ring connecting the cross die to the lower dies and including: an upper metal ring formed in a bottom surface of the cross die; and a lower metal ring formed in top surfaces of the lower dies and extending through the molding structure in the dielectric region. The lower metal ring is bonded to the upper metal ring.

Abstract: A device includes: a first integrated circuit (IC) die; a first dielectric material around first sidewalls of the first IC die; a second IC die over and electrically coupled to the first IC die; and a second dielectric material over the first dielectric material and around second sidewalls of the second IC die, where in a top view, the second sidewalls of the second IC die are disposed within, and are spaced apart from, the first sidewalls of the first IC die.

Abstract: A semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The conductive feature is electrically connected to the functional die. The seal ring is disposed aside the conductive feature. The alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.

Abstract: Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.

Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A semiconductor structure includes a first die, a first encapsulant, a second die and a second encapsulant. The first die includes a first dielectric layer and first conductive pads in the first dielectric layer. The first encapsulant laterally encapsulates and is in direct contact with the first dielectric layer of the first die. The second die includes a second dielectric layer and second conductive pads in the second dielectric layer. The second encapsulant laterally encapsulates and is in direct contact with the second dielectric layer of the second die. The first conductive pads of the first die are in physical contact with a first portion of the second conductive pads of the second die.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.

Abstract: A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure.