Patents by Inventor Ting Hou
Ting Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250103751Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.Type: ApplicationFiled: September 26, 2024Publication date: March 27, 2025Applicant: Industrial Technology Research InstituteInventors: Bo-Cheng Chiou, Chih-Sheng Lin, Tuo-Hung Hou, Chih-Ming Lai, Yun-Ting Ho, Shan-Ming Chang
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Publication number: 20250093593Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.Type: ApplicationFiled: January 3, 2024Publication date: March 20, 2025Inventors: Wen-Chih Lin, Cheng-Yu Kuo, Yen-Hung Chen, Hsuan-Ting Kuo, Chia-Shen Cheng, Chao-Wei Li, Ching-Hua Hsieh, Wen-Chih Chiou, Ming-Fa Chen, Shang-Yun Hou
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Patent number: 12250572Abstract: The present disclosure provides a signal transmission method and a signal transmission device. The signal transmission method includes: transmitting a first reference signal, the first reference signal indicating that the first network device is subjected to remote interference; and receiving a second reference signal, the second reference signal indicating that there is the remote interference and/or atmospheric ducting phenomenon.Type: GrantFiled: July 26, 2019Date of Patent: March 11, 2025Assignees: China Mobile Communication Co., Ltd Research Institute, China Mobile Communications Group Co., Ltd.Inventors: Jing Jin, Xiaodong Xu, Hua Shao, Ting Ke, Xueying Hou, Jianjun Liu
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Publication number: 20250066812Abstract: The present invention provides a polynucleotide and recombinant AAV encoding human alpha galactosidase A. The present invention also provides a method of treating Fabry disease comprising administering the recombinant AAV to a subject in need thereof.Type: ApplicationFiled: December 30, 2022Publication date: February 27, 2025Applicant: Skyline Therapeutics LimitedInventors: Jinzhao HOU, Ting YU, Jiao YUE, Haiyan JIANG
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Publication number: 20250041218Abstract: The present invention provides a method of preventing or treating CNS diseases. The method comprises the step of administering to a subject in need thereof an effective amount of (i) a polymer-flavonoid conjugate, (ii) a flavonoid oligomer, or (iii) micelles having an outer shell comprising one or more polymer-flavonoid conjugates and optionally an inner shell comprising one or more flavonoid oligomer and a drug encapsulated within the shells. The present method brings therapeutic effective materials through blood-brain barrier to treat CNS diseases. The present method is effective to treat CNS diseases such as brain tumors, stroke, neurodegenerative diseases.Type: ApplicationFiled: October 17, 2024Publication date: February 6, 2025Inventors: Chun-Ting Cheng, Yuan-Chung Tsai, Pauline Ying Lau, Kuo-Liang Hou
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Publication number: 20250031436Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure. Each of the first fin structure and the second fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure. The method also includes forming a gate stack wrapped around the first fin structure and the second fin structure. The method further includes simultaneously removing the sacrificial layers of the first fin structure and the second fin structure. Remaining portions of the semiconductor layers of the first fin structure form multiple first semiconductor nanostructures, and remaining portions of the semiconductor layers of the second fin structure form multiple second semiconductor nanostructures. Each of the first semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.Type: ApplicationFiled: July 20, 2023Publication date: January 23, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih HOU, Feng-Ming CHANG, Chun-Jun LIN, Kao-Ting LAI, Jhon-Jhy LIAW
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Publication number: 20250024383Abstract: This disclosure provides systems, methods, and devices for wireless communication that support transmission of power limit indications for a UE associated with different frequency bands. In a first aspect, a method of wireless communication includes detecting a first trigger condition for transmission of at least a first indication of a first transmission power limit of the UE and a second indication of a second transmission power limit of the UE, wherein the first transmission power limit is associated with a first frequency band supported by the UE and the second transmission power limit is associated with a second frequency band supported by the UE and transmitting, to a first network node associated with the first frequency band, the first indication and the second indication in accordance with detection of the first trigger condition. Other aspects and features are also claimed and described.Type: ApplicationFiled: July 11, 2023Publication date: January 16, 2025Inventors: Chan-Jui Chian, Chia-Wei Chang, Tzui Lu, Tsung-Te Hou, Kai-Chun Huang, Wei-Che Chang, Yuwei Pan, Cheng-Ting Tsai
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Patent number: 12132315Abstract: The present disclosure provides a parameter design method for a series passive impedance adapter applicable to a VSC-HVDC transmission system, to resolve the technical problem that high-frequency resonance may occur when impedance of a VSC-HVDC transmission system is mismatched with that of a sending-end or receiving-end grid. A parameter design goal of the present disclosure is that reactive power consumed by a series passive impedance adapter is not more than A times rated power of a converter, and a loss of the series passive impedance adapter in a fundamental wave is B times the rated power of the converter. The parameter design method for a series passive impedance adapter applicable to a VSC-HVDC transmission system in the present disclosure can realize a positive impedance characteristic within a concerned frequency band and completely eliminate a risk of harmonic resonance.Type: GrantFiled: June 6, 2021Date of Patent: October 29, 2024Assignees: ELECTRIC POWER RESEARCH INSTITUTE. CHINA SOUTHERN POWER GRID, CHINA SOUTHERN POWER GRIDInventors: Hong Rao, Changyue Zou, Shukai Xu, Yan Li, Xiaobin Zhao, Weiwei Li, Junjie Feng, Shuangfei Yang, Ting Hou, Lingfei Li, Yuke Ji
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Publication number: 20240318319Abstract: A mask manufacturing method includes a step of providing a metal substrate having a plurality of virtual zones on its surface, using a plurality of nozzles to spray an etching solution on the surface, wherein the virtual zones include a first and a second zone, and the metal substrate has a first thickness and a second thickness respectively in an unit area of the first zone and the second zone, wherein the first thickness is greater than the second thickness; the step of using the nozzles to spray the etching solution on the surface further includes respectively using a first spraying pressure and a second spraying pressure to spray the etching solution on the first zone and the second zone, and the first spraying pressure is greater than the second spraying pressure. The invention also provides a mask manufacturing device.Type: ApplicationFiled: May 27, 2024Publication date: September 26, 2024Inventors: Kuan-Ting Hou, Syue-Wun Fu
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Patent number: 12077870Abstract: A mask manufacturing method includes a step of providing a metal substrate having a plurality of virtual zones on its surface, using a plurality of nozzles to spray an etching solution on the surface, wherein the virtual zones include a first and a second zone, and the metal substrate has a first thickness and a second thickness respectively in an unit area of the first zone and the second zone, wherein the first thickness is greater than the second thickness; the step of using the nozzles to spray the etching solution on the surface further includes respectively using a first spraying pressure and a second spraying pressure to spray the etching solution on the first zone and the second zone, and the first spraying pressure is greater than the second spraying pressure. The invention also provides a mask manufacturing device.Type: GrantFiled: January 19, 2022Date of Patent: September 3, 2024Assignee: DARWIN PRECISIONS CORPORATIONInventors: Kuan-Ting Hou, Syue-Wun Fu
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Publication number: 20240204528Abstract: The present disclosure provides a parameter design method for a series passive impedance adapter applicable to a VSC-HVDC transmission system, to resolve the technical problem that high-frequency resonance may occur when impedance of a VSC-HVDC transmission system is mismatched with that of a sending-end or receiving-end grid. A parameter design goal of the present disclosure is that reactive power consumed by a series passive impedance adapter is not more than A times rated power of a converter, and a loss of the series passive impedance adapter in a fundamental wave is B times the rated power of the converter. The parameter design method for a series passive impedance adapter applicable to a VSC-HVDC transmission system in the present disclosure can realize a positive impedance characteristic within a concerned frequency band and completely eliminate a risk of harmonic resonance.Type: ApplicationFiled: June 6, 2021Publication date: June 20, 2024Inventors: Hong Rao, Changyue Zou, Shukai Xu, Yan Li, Xiaobin Zhao, Weiwei Li, Junjie Feng, Shuangfei Yang, Ting Hou, Lingfei Li, Yuke Ji
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Publication number: 20240105707Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a trench extending into a substrate, in a top view, the trench extends lengthwise along a first direction, forming a material layer over the substrate and intersecting a first portion of the trench, after the forming of material layer, forming a first capacitor intersecting a second portion of the trench, the first capacitor comprising a first plurality of conductor plates, and forming a second capacitor intersecting a third portion of the trench, the second capacitor comprising a second plurality of conductor plates, where the first plurality of conductor plates and the second plurality of conductor plates are in direct contact with the material layer.Type: ApplicationFiled: March 22, 2023Publication date: March 28, 2024Inventors: Fu-Chiang Kuo, Meei-Shiou Chern, Jyun-Ting Hou
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Publication number: 20240079353Abstract: A semiconductor device with capacitive structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, first and second trenches disposed in the substrate and separated from each other by a substrate region of the substrate, first, second, and third conductive layers disposed in the first and second trenches and on the substrate region in a stacked configuration, a nitride layer including first and second nitride portions disposed on the first and second trenches and on the substrate region, and first and second contact structures configured to provide first and second voltages to the first and second conductive layers. The first nitride portion is disposed on the first conductive layer and on sidewalls of the second and third conductive layers. The second nitride portion is disposed on the second conductive layer and on sidewalls of the third conductive layers.Type: ApplicationFiled: March 30, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Chiang KUO, Meei-Shiou Chern, Jyun-Ting Hou
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Publication number: 20230369213Abstract: A semiconductor device includes a substrate including a first trench that extends along a first lateral direction and a second trench that extends along a second lateral direction; a first metal layer filling each of the first and second trenches; a second metal layer filling each of the first and second trenches, and disposed above and electrically isolated from the first metal layer; a first via structure in electrical contact with first metal layer; and a second via structure in electrical contact with second metal layer. When viewed from the top, the first via structure and the second via structure are interposed between the first trench and the second trench along the first lateral direction. The first via structure and the second via structure are disposed immediately adjacent to each other along the second lateral direction.Type: ApplicationFiled: February 15, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chiang Kuo, Meei-Shiou Chern, Jyun-Ting Hou
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Publication number: 20230170860Abstract: The present disclosure discloses a Doherty power amplifier, including at least one carrier power amplifier and at least one peak power amplifier connected in parallel, each carrier power amplifier includes at least one carrier power amplifier unit connected in parallel for power combination, and each peak power amplifier includes at least one peak power amplifier unit connected in parallel for power combination, each of the carrier power amplifier unit and the peak power amplifier unit includes two power amplifier circuits connected in parallel for power combination, and each of the two power amplifier circuits includes a medium-low power amplifier transistor having saturation power less than or equal to a preset threshold. The present disclosure further discloses a power amplification method.Type: ApplicationFiled: June 22, 2021Publication date: June 1, 2023Inventors: Huazhang CHEN, Xiaojun CUI, Ting HOU, Jinyuan AN
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Publication number: 20230097644Abstract: An ultrasound-assisted simulated digestion method of a milk protein active peptide and an application thereof in health foods, pertaining to the technical field of intensive processing of dairy products and preparation of health foods. The method firstly employs ultrasonic pretreatment of casein and ?-lactoglobulin, followed by enzymatic hydrolysis with a protease to prepare casein and ?-lactoglobulin polypeptide, and traces the activity of the polypeptide by simulating gastrointestinal digestion, and then simulates absorption by intestinal epithelial cells with Caco-2 cells, to characterize a highly active milk protein polypeptide digested by the gastrointestinal tract and absorbed by the Caco-2 cells simulating absorption by the inner wall of the small intestine. The method has identified five such highly active milk protein polypeptides.Type: ApplicationFiled: August 5, 2022Publication date: March 30, 2023Inventors: Xiaofeng REN, Qiufang LIANG, Haile MA, Yuqing DUAN, Ronghai HE, Xiaoming YANG, Xi ZHANG, Ting HOU, Xinxiang CHEN
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Patent number: 11524977Abstract: An ultrasound-assisted simulated digestion method of a milk protein active peptide and an application thereof in health foods, pertaining to the technical field of intensive processing of dairy products and preparation of health foods. The method firstly employs ultrasonic pretreatment of casein and ?-lactoglobulin, followed by enzymatic hydrolysis with a protease to prepare casein and ?-lactoglobulin polypeptide, and traces the activity of the polypeptide by simulating gastrointestinal digestion, and then simulates absorption by intestinal epithelial cells with Caco-2 cells, to characterize a highly active milk protein polypeptide digested by the gastrointestinal tract and absorbed by the Caco-2 cells simulating absorption by the inner wall of the small intestine. The method has identified five such highly active milk protein polypeptides.Type: GrantFiled: November 12, 2018Date of Patent: December 13, 2022Assignee: JIANGSU UNIVERSITYInventors: Xiaofeng Ren, Qiufang Liang, Haile Ma, Yuqing Duan, Ronghai He, Xiaoming Yang, Xi Zhang, Ting Hou, Xinxiang Chen
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Publication number: 20220364241Abstract: A mask manufacturing method includes a step of providing a metal substrate having a plurality of virtual zones on its surface, using a plurality of nozzles to spray an etching solution on the surface, wherein the virtual zones include a first and a second zone, and the metal substrate has a first thickness and a second thickness respectively in an unit area of the first zone and the second zone, wherein the first thickness is greater than the second thickness; the step of using the nozzles to spray the etching solution on the surface further includes respectively using a first spraying pressure and a second spraying pressure to spray the etching solution on the first zone and the second zone, and the first spraying pressure is greater than the second spraying pressure. The invention also provides a mask manufacturing device.Type: ApplicationFiled: January 19, 2022Publication date: November 17, 2022Inventors: Kuan-Ting Hou, Syue-Wun Fu
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Patent number: 10842906Abstract: An air purifier includes a upper cover, having at least one grid column on front terminal of the upper cover; a bottom cover, having at least one grid column on front terminal of the bottom cover; and two groups of ultraviolet light emitting diodes (LEDs), respectively having a heat sink and a ultraviolet light emitting diode (LED), wherein the ultraviolet LED is mounted on the heat sink, and a wavelength range of the ultraviolet LED is between 100 nm and 480 nm; wherein the grid column on front terminal of the upper cover is combined with the grid column on front terminal of the bottom cover to form a column hole through which an air flows out.Type: GrantFiled: December 4, 2018Date of Patent: November 24, 2020Inventor: Jin-Ting Hou
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Patent number: D987712Type: GrantFiled: December 31, 2020Date of Patent: May 30, 2023Inventor: Wei Ting Hou