Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.

Abstract: An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The backside semiconductor structure may have one or more different materials from the semiconductor structure. For instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. As another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure.

Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure.

Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

Abstract: Integrated circuit structures having reduced local layout effects, and methods of fabricating integrated circuit structures having reduced local layout effects, are described. For example, an integrated circuit structure includes an NMOS region including a first plurality of fin structures or vertical stacks of horizontal nanowires, and first alternating gate lines and trench contact structures over the first plurality of fin structures or vertical stacks of horizontal nanowires. The integrated circuit structure also includes a PMOS region including a second plurality of fin structures or vertical stacks of horizontal nanowires, and second alternating gate and trench contact structures over the second plurality of fin structures or vertical stacks of horizontal nanowires. A gate line is shared between the NMOS region and the PMOS region, and a trench contact structure is shared between the NMOS region and the PMOS region.

Abstract: Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.

Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

Abstract: Techniques are provided to form semiconductor devices where portions of the gate structure (e.g., foot structures) adjacent to the subfins have been removed. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut includes dielectric lobe structures that extend outwards from the sidewalls of the gate cut. The lobe structures effectively replace foot structures of the gate structure between the gate cut and subfin portions of the semiconductor fins. Removing the gate foot structures contributes to the reduction of the parasitic capacitance in the semiconductor device.

Abstract: Techniques are provided to form semiconductor devices that include through-gate structures (e.g., gate cut structures or conductive via structures) that have an airgap spacer between the structure and the adjacent gate electrode. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. A through-gate structure may extend in a third direction through an entire thickness of the gate structure and adjacent to the semiconductor region along the second direction. The through-gate structure may be a dielectric structure (e.g., a gate cut) or a conductive structure (e.g., a via). In either case, an airgap spacer exists between the through-gate structure and the gate structure.

Abstract: An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.

Abstract: Transistors and integrated circuitry including a 2D channel material layer within a stack of material layers further including one or more insulator (e.g., dielectric) materials above and/or below the 2D channel material layer. These supporting insulator layers may be non-sacrificial while other material layers within a starting material stack may be sacrificial, replaced, for example, with gate insulator and/or gate material. In some exemplary embodiments, the 2D channel material is a metal chalcogenide and the supporting insulator layer is advantageously a dielectric material composition having a low dielectric constant.

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.

Abstract: Embodiments disclosed herein include transistors and methods of forming transistors. In an embodiment, a transistor comprises a source, a drain, and a pair of spacers between the source and the drain. In an embodiment, a semiconductor channel is between the source and the drain, where the semiconductor channel passes through the pair of spacers. In an embodiment, the semiconductor channel has a first thickness within the pair of spacers and a second thickness between the pair of spacers, where the second thickness is less than the first thickness. In an embodiment, the transistor further comprises a gate stack over the semiconductor channel between the pair of spacers.

Abstract: Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.

Abstract: Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.