Abstract: A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.

Abstract: A voltage mode transmitter is provided. The voltage mode transmitter includes a control unit and a resistor ladder circuit. The control unit receives a first signal and delays an inverse of the first signal for a time period to obtain a second signal. The resistor ladder circuit is configured to sum up products of the first signal or the second signal and a plurality of weights, thereby generating an output signal. The resistor ladder circuit includes an input terminal, multiple first resistors and a second resistor. The output terminal is configured to output the output signal. Each of the first resistors is coupled between the output terminal and the control unit and receives the first signal or the second signal. The resistances of the first resistors are 2R, 4R . . . and 2nR respectively, where R is a reference resistance. The resistance of the second resistor is 2nR.

Abstract: A voltage mode transmitter is provided. The voltage mode transmitter includes a control unit and a resistor ladder circuit. The control unit receives a first signal and delays an inverse of the first signal for a time period to obtain a second signal. The resistor ladder circuit is configured to sum up products of the first signal or the second signal and a plurality of weights, thereby generating an output signal. The resistor ladder circuit includes an input terminal, multiple first resistors and a second resistor. The output terminal is configured to output the output signal. Each of the first resistors is coupled between the output terminal and the control unit and receives the first signal or the second signal. The resistances of the first resistors are 2R, 4R . . . and 2nR respectively, where R is a reference resistance. The resistance of the second resistor is 2nR.

Abstract: A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a phase interpolator, a finite state machine, and a divisor-controllable frequency divider. The phase detector compares an input data signal with a frequency dividing signal and generates a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal. The phase interpolator performs phase interpolation on first and second clock signals received by the phase interpolator, so as to generate a phase interpolation signal. The finite state machine coupled to the phase detector and the phase interpolator generates the control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider coupled to the phase detector and the phase interpolator divides the second frequency of the phase interpolation signal by a divisor so as to generate the frequency dividing signal. A CDR method is also provided.

Abstract: A voltage mode transmitter includes a resistive network and a de-emphasis value controller. The resistive network receives plural input voltages and provides plural weighting values corresponding to respective input voltages. A sum of the products of the plural input voltages and the corresponding weighting values is equal to an output voltage. The de-emphasis value controller receives a first signal. After the first signal is inverted as an inverted first signal and the inverted first signal is delayed for a time period, the de-emphasis value controller generates a second signal. The de-emphasis value controller further receives a value control signal. At least one of the plural input signals is provided by the first signal and at least one of the plural input signals is provided by the second signal according to the value control signal.

Abstract: A squelch detector receives a first input signal, a second input signal, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal pair. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal pair is valid or not.

Abstract: A squelch detector receives a first input signal, a second input signal VM, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal is valid.

Abstract: A voltage mode transmitter includes a resistive network and a de-emphasis value controller. The resistive network receives plural input voltages and provides plural weighting values corresponding to respective input voltages. A sum of the products of the plural input voltages and the corresponding weighting values is equal to an output voltage. The de-emphasis value controller receives a first signal. After the first signal is inverted as an inverted first signal and the inverted first signal is delayed for a time period, the de-emphasis value controller generates a second signal. The de-emphasis value controller further receives a value control signal. At least one of the plural input signals is provided by the first signal and at least one of the plural input signals is provided by the second signal according to the value control signal.

Abstract: The present invention discloses a unitized charging and discharging battery management system and a programmable battery management module thereof The unitized charging and discharging battery management system includes a smart battery module and a programmable battery management module, which has a universal loop and a control unit. The smart battery module has at least two smart batteries which are electrically connected by a plurality of switches and circuits of the universal loop to form a charging/discharging loop in series/parallel. The control unit monitors the charging and discharging status of the smart batteries to turn on or off the switches accordingly, so as to manage the smart batteries, thereby enhancing the overall power efficacy of the smart battery module. Besides, the service life of the smart battery module is also prolonged due to the simultaneous charging and discharging capability.

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2?. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Abstract: A programmable frequency divider with a full dividing range includes a plurality of cascaded 2/1 frequency dividers. Each of the 2/1 frequency dividers has a first input node, a first output node, a second input node, a second output node and a third input node. The first input node receives a first clock signal divided by the 2/1 frequency divider and outputted as a second clock signal through the first output node. A second logical signal is generated according to the second clock signal, the first clock signal and a first logical signal received from the second input node. The 2/1 frequency divider selectively switches to perform a divide-by-two or divide-by-one operation according to the second logical signal and a first divisor signal received from the third input nodes. The programmable frequency divider provides the full dividing range as the result of utilizing various divisor of the 2/1 frequency divider.

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2?. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Abstract: A phase-controlled current source for phase-locked loop is provided. The phase-locked loop includes a voltage-controlled oscillator to associate a charging path or discharging path in order to generate an output signal and the output signal is further sensed so as to generate a loop signal. The phase-controlled current source includes a status memory receiving the loop signal and the reference signal so as to output an energy-triggering/energy-removing signal; and a controllable current source, under the control by energy-triggering/energy-removing signal so as to decide whether a charging and discharging action should be performed, wherein after the charging action or discharging action is decided, the charging path or the discharging path is generated through the reference signal and the loop signal.

Abstract: A phase-controlled current source for phase-locked loop, the phase-locked loop comprises of a voltage-controlled oscillator to associate a charging path or discharging path in order to generate an output signal and the output signal is further sensed so as to generate a loop signal, then, together with a reference signal, these signals are used to control phase-controlled current source. Phase-controlled current source comprises of a status memory and a controllable current source and the status memory receives reference signal and loop signal in order to generate an energy-triggering/energy-removing signal, controllable current source then follows the energy-triggering/energy-removing signal to decide if to perform charging or discharging behavior; after charging or discharging behavior is decided, loop signal will decide the charging path or discharging path for the controllable current source based on reference signal so as to perform charging or discharging behavior.