Abstract: The present invention provides a wireless communication method of an electronic device, wherein the electronic device includes a first radio and a second radio, a maximum bandwidth or a maximum. NSS supported by the first radio is different from a maximum bandwidth or a maximum NSS supported by the second radio. The wireless communication method includes the step of: using the first radio to communicate with another electronic device; determining if parameters of the electronic device satisfy a condition; and in response to the parameters of the electronic device satisfying the condition, enabling the second radio and using the second radio to communicate with the another electronic device, and disabling the first radio.

Abstract: An antenna structure is provided, which includes a substrate, an antenna unit and a metal ground. The substrate includes a first surface and a second surface; the antenna unit disposed on the first surface includes a radiation part, a feeding part and a feeding line, where the feeding line includes a first transmission line and a second transmission line that are perpendicular to each other and connected to each other, and the first transmission line is connected to the radiation part via the feeding part; and the metal ground disposed on the second surface has an edge which is perpendicular to projection of the radiation part to the metal ground; and a resonance slot is disposed on the metal ground, and its position corresponds between projection of the second transmission line to the metal ground and the edge.

Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.

Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.

Abstract: An additive type bio-decomposable composite is prepared by: mixing a synthesized bio-decomposable resin with refined sodium sulphate and additives in a high-low temperature mixing pot at a high mixing, and then crushing the mixture thus obtained and delivering the crushed mixture to a double-screw extruding machine for processing through blending, granulation and cooling steps into a white, uniform, grained, finished product. The additive type bio-decomposable composite thus prepared can be used with any of a variety of plastic materials for making decomposable plastic products that, when become waste after service, will decompose gradually under a variety of natural environmental conditions and return to nature. Therefore, the use of the additive type bio-decomposable composite in accordance with the present invention can reduce pollution and save the plastic material cost and meet environmentally friendly requirements.

Abstract: A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.

Abstract: A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.

Abstract: The present invention discloses a method for crosstalk elimination in high-performance processors. The method, based on the combination of a deassembler and an assembler, eliminates crosstalk with fewer extra wires. The method of the present invention includes the steps of: deassembling a first piece of data to a plurality of data segments; conducting a parallel crosstalk check on the data segments to form a second piece of data that is crosstalk-free; and restoring the first piece of data based on the second piece of data. The present invention also discloses a bus architecture performing the method for crosstalk elimination, which includes a deassembler, a transmission bus and an assembler.

Abstract: A socket provided with a ratchet device comprises: a polygon-shaped end portion, a ratchet device having a receiving groove provided with a plurality of retaining walls and guiding walls, a plurality of retaining members and springs, a direction-controlling sleeve having a plurality of protruded portions therebottom, and a coupling bar. At one end of the socket is formed the polygon-shaped end portion, while at another end is defined with the ratchet device. The receiving groove is formed at the upper end of socket for receiving a plurality of retaining members and springs therein.

Abstract: Disclosed is a sectionless length adjustment mechanism for the shank of a tool (e.g., screwdriver) and for releasably locking the shank in any one of a plurality of positions relative to the handle. In one embodiment the mechanism comprises a sleeve having a front flared end, a spring anchored in the sleeve, a shell including two opposite bars on its surface, and a nut secured to the sleeve. Pulling the shank forward will move the bars outward forward along the flared end to expand the spring. Pushing the shank rearward will move the bars inward rearward along the flared end to compress the spring. Stopping sliding will lockingly engage the shank. Loosening the nut will move the shell forward and expand the spring until the shank is free to slide with the bars disposed at a mouth of the flared end and disengaged from the shank.

Abstract: Disclosed is a sectionless length adjustment mechanism for the shank of a tool (e.g., screwdriver) and for releasably locking the shank in any one of a plurality of positions relative to the handle. In one embodiment the mechanism comprises a sleeve having a front flared end, a spring anchored in the sleeve, a shell including two opposite bars on its surface, and a nut secured to the sleeve. Pulling the shank forward will move the bars outward forward along the flared end to expand the spring. Pushing the shank rearward will move the bars inward rearward along the flared end to compress the spring. Stopping sliding will lockingly engage the shank. Loosening the nut will move the shell forward and expand the spring until the shank is free to slide with the bars disposed at a mouth of the flared end and disengaged from the shank.

Abstract: An improved method for selecting etch endpoint when dry etching conductive material layers for use in semiconductor device circuits has been created. The more precise endpoint selection procedure produces metallization patterns which are free from residues (resulting from under-etching) and free from sidewall attack and/or pattern degradation (resulting from over-etching). The method avoids costly and time consuming pre-sorting of substrates according to product pattern density.

Abstract: A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.

Abstract: A method and apparatus for applying a liquid to the surface of semiconductor wafer are described. The wafer is rotated about an axis; perpendicular to its main surface. Liquid is dispensed onto the surface of the spinning wafer from at least two dispensing bottles. One of the dispensing bottles is positioned above the center of rotation while the others are located between it and the wafer's edge. The rate at which liquid emerges from each of the dispensing bottles is independently controlled for each bottle.

Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the polycide peeling problems. A pattern of gate electrode structures is formed upon a semiconductor substrate which each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. This causes the formation of a thin layer of silicon dioxide upon the exposed silicon substrate, the exposed polysilicon layer and the exposed metal silicide layer. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces and spacer structures formed by anisotropic etching.

Abstract: Disclosed is a method of integrated circuit manufacture involving a method for optimizing the time needed to outgas a layer of spin-on-glass. A layer of spin-on-glass that was previously covered over may be exposed again as a result of subsequent processing. It is necessary to subject such a layer to an outgassing treatment by heating it in vacuum prior to the deposition of a metal film which could react with any ougassed material that was not already removed. To avoid having to heat the integrated circuit for any longer than is absolutely necessary during outgassing, the partial pressure of the outgassed material is monitored by means of a residual gas analyzer whose output is used to control the outgassing process.

Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which provides a peeling-free metal silicide gate electrode devices. The process uses annealing of the gate oxide, the polysilicon layer and the metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000.degree. C. and for a time of between about 30 to 60 seconds. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Driving in the pattern of lightly doped regions is accomplished by rapid thermal annealing at a temperature of more than about 1000.degree. C.

Abstract: A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.

Abstract: The method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less is accomplished by first providing an integrated circuit structure having device elements within a semiconductor substate and multilayer insulating layers thereover. A resist masking layer is formed over the multilayer insulating layer having openings therein in the areas where the contact openings are desired. Isotropic etching is done through a desired thickness portion of multilayer insulating layer. Anisotropic etching is now done through the remaining thickness of multilayer insulating layer to the semiconductor substrate to form the desired contact opening. The resist layer is removed. The structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of multilayer layer and the point where the isotropic etching ended and the anisotropic etching began.