Patents by Inventor Ting-Kuei Kuan
Ting-Kuei Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11201625Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider and a track-and-hold charge pump. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to provide a feedback signal according to the output clock. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The track-and-hold charge pump includes a track-and-hold circuit, a pumping switch and a pulse width modulator (PWM). The track-and-hold circuit is coupled to the frequency divider and configured to sample the feedback signal according to the reference clock. The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the sampled feedback signal.Type: GrantFiled: October 13, 2020Date of Patent: December 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Kuei Kuan, Cheng-Hsiang Hsieh, Chen-Ting Ko, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20210028789Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider and a track-and-hold charge pump. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to provide a feedback signal according to the output clock. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The track-and-hold charge pump includes a track-and-hold circuit, a pumping switch and a pulse width modulator (PWM). The track-and-hold circuit is coupled to the frequency divider and configured to sample the feedback signal according to the reference clock. The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the sampled feedback signal.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventors: Ting-Kuei KUAN, Cheng-Hsiang HSIEH, Chen-Ting KO, Ruey-Bin SHEEN, Chih-Hsien CHANG
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Patent number: 10855292Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.Type: GrantFiled: December 20, 2019Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ting-Kuei Kuan, Cheng-Hsiang Hsieh, Chen-Ting Ko, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20200127668Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Inventors: Ting-Kuei KUAN, Cheng-Hsiang HSIEH, Chen-Ting KO, Ruey-Bin SHEEN, Chih-Hsien CHANG
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Patent number: 10523218Abstract: Track-and-hold charge pumps and PLL are provided. A track-and-hold charge pump includes a track-and-hold circuit, a transconductance amplifier, a pulse width modulator (PWM), and a pumping switch coupled to the transconductance amplifier. The track-and-hold circuit samples an input signal according to a reference clock. The transconductance amplifier converts the sampled input signal into a current. The PWM provides a PWM signal according to the reference clock. The pumping switch is controlled by the PWM signal, to provide an output current according to the current.Type: GrantFiled: April 18, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ting-Kuei Kuan, Cheng-Hsiang Hsieh, Chen-Ting Ko, Ruey-Bin Sheen, Chih-Hsien Chang
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Patent number: 10374617Abstract: A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.Type: GrantFiled: August 31, 2017Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Ting-Kuei Kuan, Chin-Yang Wu, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20190058480Abstract: A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.Type: ApplicationFiled: August 31, 2017Publication date: February 21, 2019Inventors: TING-KUEI KUAN, CHIN-YANG WU, RUEY-BIN SHEEN, CHIH-HSIEN CHANG
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Publication number: 20180302096Abstract: Track-and-hold charge pumps and PLL are provided. A track-and-hold charge pump includes a track-and-hold circuit, a transconductance amplifier, a pulse width modulator (PWM), and a pumping switch coupled to the transconductance amplifier. The track-and-hold circuit samples an input signal according to a reference clock. The transconductance amplifier converts the sampled input signal into a current. The PWM provides a PWM signal according to the reference clock. The pumping switch is controlled by the PWM signal, to provide an output current according to the current.Type: ApplicationFiled: April 18, 2017Publication date: October 18, 2018Inventors: Ting-Kuei KUAN, Cheng-Hsiang HSIEH, Chen-Ting KO, Ruey-Bin SHEEN, Chih-Hsien CHANG
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Patent number: 9831880Abstract: Systems and methods for automatically controlling one or more parameters of a digital phase-locked loop (DPLL) circuit are provided. A phase error signal generated by a phase detector of the DPLL circuit is received. A delayed version of the phase error signal is generated. A product of the phase error signal and the delayed version of the phase error signal is generated. The product is integrated, and a first output for controlling a gain of a proportional path of the DPLL circuit is generated based on the integrated product. The first output is down-sampled. A least-mean-square (LMS) filter is used to generate a second output that minimizes a value of the down-sampled output. A gain of an integral path of the DPLL is controlled based on the second output.Type: GrantFiled: July 27, 2016Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Ting-Kuei Kuan