Abstract: A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total cycles; comparing the latencies of each access request and total cycles respectively, if the total cycles is larger than the latency of a request, then arranging one more the same request in the priority queue, else executing the priority queue in order.

Abstract: A method and system for applying pipeline architecture to discrete cosine transform and inverse discrete cosine transform. Each of the discrete cosine transform and inverse cosine transform are divided into four phases computed by process elements. Each phase can be designed by adjusting the amount of process elements according the demand of performance.

Abstract: An apparatus and a method for memory access of sharing the address and the data buses used in multi-media player, comprising at least one SDRAM, storing the large data and as a buffer in high speed; at least one flash memory, storing the programs, the user's defaults and firmware, wherein the address and data pins of the SDRAM and the flash memory are coupled with a same bus respectively, and SDRAM and flash memory are not accessed at the same time; a memory interface, connecting the address bus and data bus shared by the SDRAM and flash memory. The memory interface further comprises an arbiter, deciding which one of the access requests is executed according to the request priority. It is noticed that only one of the SDRAM or the flash memory can be accessed at one time.

Abstract: A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total cycles; comparing the latencies of each access request and total cycles respectively, if the total cycles is larger than the latency of a request, then arranging one more the same request in the priority queue, else executing the priority queue in order.

Abstract: An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.

Abstract: The present invention provides a method and apparatus of adaptive de-interlacing of dynamic image, configured for calculating encoding information of a dynamic image to acquire an image shift value of field and then compare the image shift value of field with a programmable threshold. When the image shift value of field is substantially greater than the threshold, then choosing Bob algorithm for de-interlacing; otherwise, when the image shift value of field is substantially less than the threshold, then choosing Weave algorithm for de-interlacing to constitute a high-resolution motion image.

Abstract: The present invention provides a method and apparatus of adaptive de-interlacing of dynamic image, in which extraction and calculation of motion vectors contained in a macro-block being processed, the value of calculation of motion vectors being then compared with a programmable threshold; wherein the macro-block being a motion block if the value of calculation being greater than the threshold and therefore Bob algorithm being chosen for de-interlacing process. Otherwise, the macro-block being a still block if the value of calculation being less than the threshold and therefore Weave algorithm being chosen for de-interlacing process. Consequently, the process is enforced continually and a dynamic image of high image quality is constituted with block as its unit.

Abstract: An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.

Abstract: A method and a system for reducing the bandwidth access in video encoding are disclosed. The illuminance of the search area and the illuminance of the current macro block for motion estimation are fetched from a memory by a motion estimation module. The motion estimation is performed by finding the illuminance of a most fitted macro block which best matches the illuminance of the current macro block. Then a motion compensation module fetches the chrominance of the current macro block and the chrominance of the most fitted macro block from the memory to complete the attributes of the current macro block and the most fitted macro block separately. The motion compensation is performed according to the most fitted macro block and the current macro block by the motion compensation module. Thus, the illuminance of the current macro block and the most fitted macro block are reused in the motion compensation for reducing the memory bandwidth access.

Abstract: A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total cycles; comparing the latencies of each access request and total cycles respectively, if the total cycles is larger than the latency of a request, then arranging one more the same request in the priority queue, else executing the priority queue in order.

Abstract: A device and a method of sharing IDCT are disclosed. Firstly, a data word and an identifier for representing which one of several formats are extracted from a received word. Then the data word is treated with IDCT to be a signed word afterward. Then the signed word is transformed into a formatted word between the values of a maximum value and a minimum value. The data word and identifier can be received by a word receiving means and treated with IDCT by an IDCT means to generate a signed word. The signed word is transformed into a formatted word for outputting via a word transforming means. Such that words with different formats can be treated with a sharing IDCT to save the redundant cost.

Abstract: A multiplying apparatus and method based on Booth's algorithm are disclosed. According to a multiplier index, a one of several predetermined multiplier coefficient sets can be chosen. Each multiplier coefficient set contains several multiplier coefficients that are generated according to a predetermined multiplier value by Booth's algorithm. Then the multiplier coefficients can be used to generate the partial products according to a multiplicand by Booth's algorithm. By summing all of the partial products, an output value can be generated.

Abstract: A method and system for applying pipeline architecture to discrete cosine transform and inverse discrete cosine transform. Each of the discrete cosine transform and inverse cosine transform are divided into four phases computed by process elements. Each phase can be designed by adjusting the amount of process elements according the demand of performance.

Abstract: An apparatus and a method for memory access of sharing the address and the data buses used in multi-media player, comprising at least one SDRAM, storing the large data and as a buffer in high speed; at least one flash memory, storing the programs, the user's defaults and firmware, wherein the address and data pins of the SDRAM and the flash memory are coupled with a same bus respectively, and SDRAM and flash memory are not accessed at the same time; a memory interface, connecting the address bus and data bus shared by the SDRAM and flash memory. The memory interface further comprises an arbiter, deciding which one of the access requests is executed according to the request priority. It is noticed that only one of the SDRAM or the flash memory can be accessed at one time.

Abstract: An apparatus and method for co-simulating of processors and DUT modules comprising steps of constructing and executing a processor simulation program and a Hardware Description Language (HDL) simulation environment that is activated by a corresponding simulator, and further for executing a command processing model and the processor simulation program, and establishing a message queue as a buffer of the message and data. Whenever the intercommunication occurred, the command will be processed via a Program Language Interface (PLI), the command processing model, a message queue mechanism for I/O command, and a signal mechanism for interrupt command.

Abstract: A method for flash cards access is provided, said method comprises detecting signals from specific pins of slots of flash cards and determining flash card insertion according to said signals. Said method further comprises disabling flash cards by sending signals for at least one pin of other flash cards' slots.

Abstract: A detecting device for determining type and insertion of flash memory card is provided, which comprises a flash memory card interface which comprises a plurality of flash memory card slots, a control module detecting signals transmitted from the plurality of flash memory card slots and a bus which comprises a plurality of detecting wires and a plurality of signal wires, wherein one side of each detecting wire is respectively connected to detect pin of each flash memory card slot, and the other side is respectively connected to the control module, one side of each signal wire is connected to all data pins of those flash memory card slots in a predetermined corresponding way, and the other side is connected to the control module.

Abstract: The present invention provides a method and apparatus of adaptive de-interlacing of dynamic image, in which extraction and calculation of motion vectors contained in a macro-block being processed, the value of calculation of motion vectors being then compared with a programmable threshold; wherein the macro-block being a motion block if the value of calculation being greater than the threshold and therefore Bob algorithm being chosen for de-interlacing process. Otherwise, the macro-block being a still block if the value of calculation being less than the threshold and therefore Weave algorithm being chosen for de-interlacing process. Consequently, the process is enforced continually and a dynamic image of high image quality is constituted with block as its unit.

Abstract: The present invention provides a method and apparatus of adaptive de-interlacing of dynamic image, configured for calculating encoding information of a dynamic image to acquire an image shift value of field and then compare the image shift value of field with a programmable threshold. When the image shift value of field is substantially greater than the threshold, then choosing Bob algorithm for de-interlacing; otherwise, when the image shift value of field is substantially less than the threshold, then choosing Weave algorithm for de-interlacing to constitute a high-resolution motion image.