Abstract: In an aspect of the disclosure, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.

Abstract: A voltage generator adapted for a flash memory is disclosed. The voltage generator includes a charge pump circuit and a voltage regulator. The charge pump circuit includes at least one charge pump unit having a voltage receiving terminal and a voltage transmitting terminal. The voltage receiving terminal receives a reference voltage and the voltage transmitting terminal generates an output voltage. The charge pump unit includes first and second voltage transmitting channels and first and second capacitors. The first and second voltage transmitting channels are turned on or off according first and second control signals, respectively. The first and second capacitors receive the first and second pump enabling signals, respectively. The voltage regulator outputs a regulated output voltage according to the output voltage.

Abstract: A flash memory is disclosed. A core array stores data. A peripheral circuit accesses the data stored in the core array to generate read data. A off-chip driver (OCD) processes the read data to generate output data. An interconnect structure is electrically connected to the core array, the peripheral circuit, and the OCD and includes three conductive layers. The conductive layers are electrically connected to each other. An uppermost conductive layer is formed over the interconnect structure, electrically connected to the interconnect structure, and includes a first power pad and first power tracks. The first power pad is electrically connected to a power pin via a first bonding wire to receive an operation voltage. The first power tracks are electrically connected between the first power pad and the interconnect structure to transmit the operation voltage to at least one of the core array, the peripheral circuit and the OCD.

Abstract: A voltage generator adapted for a flash memory is disclosed. The voltage generator includes a charge pump circuit and a voltage regulator. The charge pump circuit includes at least one charge pump unit having a voltage receiving terminal and a voltage transmitting terminal. The voltage receiving terminal receives a reference voltage and the voltage transmitting terminal generates an output voltage. The charge pump unit includes first and second voltage transmitting channels and first and second capacitors. The first and second voltage transmitting channels are turned on or off according first and second control signals, respectively. The first and second capacitors receive the first and second pump enabling signals, respectively. The voltage regulator outputs a regulated output voltage according to the output voltage.

Abstract: A method for erasing data stored in the memory cells of the floating gate flash memory is included. The method allows a plurality of sectors to be disposed in a same P well. The method includes erasing data stored in a first set of memory cells according to a control signal, randomly reading the data stored in a second set of memory cells affected by the erasing action of the first set of memory cells, and writing data read from the second set of memory cells onto the second set of memory cells.

Abstract: A method for erasing data stored in the memory cells of the floating gate flash memory is disclosed. The method allows a plurality of sectors to be disposed in a same P well. The method includes erasing data stored in a first set of memory cells according to a control signal, randomly reading the data stored in a second set of memory cells affected by the erasing action of the first set of memory cells, and writing data read from the second set of memory cells onto the second set of memory cells.

Abstract: A method for increasing transmission efficiency of an electronic device using a serial peripheral interface includes receiving data from a first pin of the serial peripheral interface of the electronic device during a first duration according to a clock signal received from a clock pin of the serial peripheral interface of the electronic device, and outputting data from the first pin during a second duration according to the clock signal.

Abstract: A flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers. The flash memory has a row driver for driving a predetermined word line to approach a predetermined voltage level. The row driver has a plurality of word line drivers, and each word line driver has a plurality of driving units and a driving voltage output circuit. The driving voltage output circuit is used for determining operating voltage levels of a plurality of driving voltages according to a plurality of second decoded signals without utilizing a plurality of first decoded signals, and for outputting a predetermined driving voltage to drive the predetermined word line to approach the predetermined voltage level when a driving unit electrically connected to the predetermined word line is turned on for connecting the predetermined word line and the driving voltage output circuit.

Abstract: A regulated charge pump has a negative charge pump for generating a first output voltage according to an oscillation signal, and a regulator. The regulator has a level shift circuit, a differential amplifier for generating a compare signal, and an oscillator for generating the oscillation signal according to the compare signal. The level shift circuit has a plurality serially connected PMOS transistors. A first PMOS transistor has a first source connected to a first reference voltage, and a gate and a drain both connected to an output end of the level shift circuit. A second PMOS has a gate and a drain both connected to an output end of the negative charge pump.

Abstract: A flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers. The flash memory has a row driver for driving a predetermined word line to approach a predetermined voltage level. The row driver has a plurality of word line drivers, and each word line driver has a plurality of driving units and a driving voltage output circuit. The driving voltage output circuit is used for determining operating voltage levels of a plurality of driving voltages according to a plurality of second decoded signals without utilizing a plurality of first decoded signals, and for outputting a predetermined driving voltage to drive the predetermined word line to approach the predetermined voltage level when a driving unit electrically connected to the predetermined word line is turned on for connecting the predetermined word line and the driving voltage output circuit.

Abstract: A regulated charge pump has a negative charge pump for generating a first output voltage according to an oscillation signal, and a regulator. The regulator has a level shift circuit, a differential amplifier for generating a compare signal, and an oscillator for generating the oscillation signal according to the compare signal. The level shift circuit has a plurality serially connected PMOS transistors. A first PMOS transistor has a first source connected to a first reference voltage, and a gate and a drain both connected to an output end of the level shift circuit. A second PMOS has a gate and a drain both connected to an output end of the negative charge pump.