Patents by Inventor Ting Luo
Ting Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250111886Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.Type: ApplicationFiled: December 12, 2024Publication date: April 3, 2025Inventors: Li-Te Chang, Murong Lang, Zhenming Zhou, Ting Luo
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Publication number: 20250104779Abstract: Methods, systems, and devices for a ganged read operation for multiple sub-blocks are described. The method may include writing a respective first logic state to each memory cell of a set of memory portions and biasing a first word line and a second word line to a first voltage. In some examples, the first word line may correspond to a first memory portion and the second word line may correspond to a second memory portion. Further, the method may include applying a first read pulse to the first word line and a second read pulse to the second word line and reading a second logic state from one or more memory cells of the first memory portion and the second memory portion. Further, the method may include validating the write operation based on reading the second logic state from the memory cells of the first memory portion and the second memory portion.Type: ApplicationFiled: July 24, 2024Publication date: March 27, 2025Inventors: Yu-Chung Lien, Ting Luo, Zhenming Zhou
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Publication number: 20250095332Abstract: Embodiments of the present disclosure provide a method and apparatus for video processing, a device, and a medium, the method includes: distributing first shoot frames to a recording unit and a content analysis unit during a shooting process; performing a recording processing on the first shoot frames by the recording unit to obtain a recorded video; and performing a content analysis processing on the first shoot frames by the content analysis unit to obtain content analysis results of the first shoot frames; in case of obtaining the recorded video, determining a content analysis result of the recorded video based on the content analysis results of the first shoot frames; the content analysis result of the recorded video is used when performing an edit processing on the recorded video.Type: ApplicationFiled: September 22, 2023Publication date: March 20, 2025Inventors: Guangde HUANG, Zhanpeng HUANG, Xuyue HAN, Ting LUO, Yihan YANG
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Publication number: 20250091930Abstract: Disclosed is a clamping device at an edge of a substrate glass during molding based on an overflow technique and an operation method thereof. The clamping device comprises a primary clamping unit and a secondary edge drawing unit that are clamped on edges of two sides of a glass plate, respectively. The primary clamping unit is arranged above the secondary edge drawing unit and is closer to a guide plate than the secondary edge drawing unit. The operation method comprises during the molding of the glass plate, enabling clamping wheels of the primary clamping unit and wheels for cooling and edge drawing of the secondary edge drawing unit to clamp the edges of the two sides of the glass plate to make liquid glass at the edges merge and bond together to obtain a bonded glass plate; and introducing cooling air to cool edges of the bonded glass plate.Type: ApplicationFiled: December 5, 2024Publication date: March 20, 2025Applicant: CAIHONG DISPLAY DEVICES CO., LTD.Inventors: Weidong HU, Zhijun ZHANG, Yongjing REN, Ting LUO
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Publication number: 20250086282Abstract: In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.Type: ApplicationFiled: July 25, 2024Publication date: March 13, 2025Inventors: Yu-Chung LIEN, Lakshmi Kalpana K VAKATI, Dheeraj SRINIVASAN, Ting LUO, Zhenming ZHOU
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Publication number: 20250075884Abstract: A lighting apparatus includes an optical component housing, an optical component and a light source. The optical component housing has an optical container and an entrance opening. The entrance opening is disposed on a lateral side of the optical component housing. The optical component housing has a light escape side. The lateral side is at a different plane as the light escape side. The optical component is detachably inserted into the optical container via the entrance opening. a cover manually operable to reveal the entrance opening for inserting the optical component and operable to conceal the entrance opening. a light source. A light is emitted from the light source passing through the optical component and escaped from the light escape side.Type: ApplicationFiled: August 29, 2024Publication date: March 6, 2025Inventors: Tiansong Lan, Siyuan Su, Junjie Lin, Jiansheng Zhang, Haiyan Chen, Ting Luo
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Patent number: 12242734Abstract: A system comprises a memory device including a plurality of management units and a processing device. The processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.Type: GrantFiled: August 24, 2023Date of Patent: March 4, 2025Assignee: Micron Technology, Inc.Inventors: Guang Hu, Ting Luo
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Publication number: 20250054527Abstract: Methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. A memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (LP)) associated with a set of wordlines. In some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. In the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. The memory device may switch to a second mode in response to a trigger condition. In the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.Type: ApplicationFiled: August 15, 2024Publication date: February 13, 2025Inventors: Cheng Cheng Ang, Chun Lei Kong, Ting Luo, Aik Boon Edmund Yap
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Publication number: 20250046344Abstract: The present disclosure relates to a method, apparatus, device, storage medium and program product for processing multimedia data. The method comprises: acquiring first multimedia draft data, wherein the first multimedia draft data is generated based on a segmented recording operation, video materials collected by the segmented recording operation being used to form video track segments in the first multimedia draft data; importing the first multimedia draft data into a first editor, so that the video track segments are displayed on a video editing track of the first editor; updating the first multimedia draft data in response to triggering a video editing operation for the video track segments on the first editor, to obtain second multimedia draft data; and generating a target video based on the second multimedia draft data in response to a trigger operation of video synthesis.Type: ApplicationFiled: October 22, 2024Publication date: February 6, 2025Inventors: Zhanpeng HUANG, Guangde HUANG, Hengan WU, Rongtao YANG, Ting LUO, Yihan YANG, Xuyue HAN
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Publication number: 20250036307Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.Type: ApplicationFiled: October 10, 2024Publication date: January 30, 2025Inventors: Murong Lang, Christina Papagianni, Zhenming Zhou, Ting Luo
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Patent number: 12198777Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.Type: GrantFiled: July 14, 2022Date of Patent: January 14, 2025Assignee: Micron Technology, Inc.Inventors: Li-Te Chang, Murong Lang, Zhenming Zhou, Ting Luo
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Patent number: 12183407Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.Type: GrantFiled: May 4, 2022Date of Patent: December 31, 2024Assignee: Micron Technology, Inc.Inventors: Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo, Giuseppe Ferrari, Walter Di Francesco, Antonino Pollio, Luigi Esposito, Anna Scalesse, Allison J. Olson, Anna Chiara Siviero
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Publication number: 20240385751Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a program-erase cycle count associated with at least a portion of the plurality of memory cells. The processing device is further to erase, based on the value of the PEC count, less than a predetermined portion of free sets of memory cells to form an erased set of memory cells. The processing device is further to receive a programming command directed to at least a portion of the erased set of memory cells. The processing device is further to perform a programming operation with respect to the at least a portion of the erased set of memory cells.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Chun Sum Yeung, Deping He, Ting Luo, Guang Hu, Jonathan S. Parry
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Patent number: 12141467Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.Type: GrantFiled: July 19, 2022Date of Patent: November 12, 2024Assignee: Micron Technology, Inc.Inventors: Murong Lang, Christina Papagianni, Zhenming Zhou, Ting Luo
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Publication number: 20240370181Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to dynamically allocate blocks from a free block pool. The controller generates a free block pool that includes a collection of full blocks and a collection of partial good blocks (PGBs) of a set of memory components, a size of a full block in the collection of full blocks corresponding to a combination of two or more PGBs of the collection of PGBs. The controller receives a request to write data. The controller allocates an individual full block from the collection of full blocks or an individual PGB from the collection of PGBs based on determining whether the request to write the data has been received from the host device or the controller of the memory sub-system.Type: ApplicationFiled: May 1, 2024Publication date: November 7, 2024Inventors: Yuqi Zhu, Guang Hu, Ting Luo, Xiangang Luo
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Patent number: 12136444Abstract: The present disclosure relates to a method, apparatus, device, storage medium and program product for processing multimedia data. The method comprises: acquiring first multimedia draft data, wherein the first multimedia draft data is generated based on a segmented recording operation, video materials collected by the segmented recording operation being used to form video track segments in the first multimedia draft data; importing the first multimedia draft data into a first editor, so that the video track segments are displayed on a video editing track of the first editor; updating the first multimedia draft data in response to triggering a video editing operation for the video track segments on the first editor, to obtain second multimedia draft data; and generating a target video based on the second multimedia draft data in response to a trigger operation of video synthesis.Type: GrantFiled: December 26, 2023Date of Patent: November 5, 2024Assignee: Beijing Zitiao Network Technology Co., Ltd.Inventors: Zhanpeng Huang, Guangde Huang, Hengan Wu, Rongtao Yang, Ting Luo, Yihan Yang, Xuyue Han
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Patent number: 12112819Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.Type: GrantFiled: October 3, 2023Date of Patent: October 8, 2024Assignee: Micron Technology, Inc.Inventors: Sheyang Ning, Lawrence Celso Miranda, Tomoko Ogura Iwasaki, Ting Luo, Luyen Vu
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Patent number: D1051974Type: GrantFiled: May 24, 2023Date of Patent: November 19, 2024Inventors: Changhao Li, Qiang Li, Ting Luo, Shi Xiao, Bo Zhong
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Patent number: D1060144Type: GrantFiled: August 25, 2023Date of Patent: February 4, 2025Inventor: Ting Luo
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Patent number: D1061689Type: GrantFiled: September 11, 2024Date of Patent: February 11, 2025Assignee: Phicbital(Chongqing) Data Technology Co., Ltd.Inventor: Ting Luo