Abstract: A system includes a memory device having a memory array with memory cells organized into memory blocks, and a processing device coupled to the memory device. The processing device receives a programming command directed to a set of memory cells, the programming command associated with a cell type indicating a number of bits to be stored per memory cell. The processing device determines, based on the cell type, an erase mode corresponding to the cell type, and determines whether a memory block is in an erased state corresponding to the erase mode. Responsive to determining that the memory block is in the erased state corresponding to the erase mode, the processing device performs a programming operation with respect to the set of memory cells. Responsive to determining that the memory block is not in the erased state corresponding to the erase mode, the processing device erases the memory block in the erase mode prior to performing the programming operation.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to dynamically allocate blocks from a free block pool. The controller generates a free block pool that includes a collection of full blocks and a collection of partial good blocks (PGBs) of a set of memory components, a size of a full block in the collection of full blocks corresponding to a combination of two or more PGBs of the collection of PGBs. The controller receives a request to write data. The controller allocates an individual full block from the collection of full blocks or an individual PGB from the collection of PGBs based on determining whether the request to write the data has been received from the host device or the controller of the memory sub-system.

Abstract: Devices for a horizontal secondary stretching of ultra-thin flexible glass are provided. The device includes: a feeding unit, a welding unit, a preheating unit, a transverse stretching extension unit, a longitudinal traction stretching unit, an annealing unit, and a winding and wrapping unit connected in sequence. Each of the feeding unit, the welding unit, the preheating unit, the transverse stretching extension unit, the longitudinal traction stretching unit, the annealing unit, and the winding and wrapping unit is provided with an air floatation device and a roller. Each of the preheating unit, the transverse stretching extension unit, the longitudinal traction stretching unit, and the annealing unit is provided with a heating unit. Each of the longitudinal traction stretching unit and the annealing unit is provided with a cooling mechanism.

Abstract: A processing device enables a sticky read mode for a group of blocks of a memory device classified in a particular block family error avoidance (BFEA) bin among multiple BFEA bins. Based on the sticky read mode being enabled for the group of blocks, the processing device applies a sticky read offset to a default read voltage for the group of blocks. The sticky read offset is based on the particular BFEA bin in which the group of blocks is classified. The processing device performs one or more read operations on one or more blocks from the group of blocks using the default read voltage with the sticky read offset applied.

Abstract: A heating device and method for substrate glass production are provided. The device includes a furnace tray and multiple heating members. On the furnace tray's side facing the glass substrate, multiple grooves are arrayed along its height; each groove body penetrates the furnace tray along its length direction, with one heating member inside and extending along the groove body's length direction. Each heating member includes a fixing rod disposed in the groove body and fixedly mounted to the furnace tray and a heating wire wound around an outer circumferential surface of the fixing rod along a length direction of the fixing rod. In a thickness direction of the furnace tray, an outer diameter of the heating wire is greater than a height of the groove body. An inner side surface of the groove body has a reflective layer with a preset distance from the heating member.

Abstract: The present disclosure discloses overflow bricks, apparatus, and methods for stably producing substrate glass, and belongs to the technical field of manufacturing liquid crystal substrate glass. The overflow brick provided in the present disclosure adopts a split arched overflow brick structure, thereby weakening the influence of the overflow brick's own gravity on the production stability. Meanwhile, each of the support clamping devices with the L-shaped structure is introduced to counteract the negative effects of the creep by applying the clamping force horizontally.

Abstract: Methods, systems, and devices for data block refresh during read access are described. In some instances, when an access command (e.g., a read command) is received, a memory system may determine if the associated block is a PSA block. If the block is PSA block, its data may be provided to a host system to satisfy the read command and the block may either be refreshed or may be designated to be refreshed. For example, the block may be refreshed by copying its data to a write cache and writing the data from the cache to a new block. In other instances, an LBA of the block may be stored (e.g., designated) and the LBA may be refreshed when the memory system is idle.

Abstract: A device and a method for conveying molten glass are provided. The device for conveying molten glass includes: a conduit structure, and at least one of a first cooling system or a second cooling system. The conduit structure axially penetrates through a throat in a throat brick to form a transmission channel for a glass fluid, the conduit structure including at least one metal conduit; the first cooling system is disposed on an inner wall of the throat and is not in direct contact with the conduit structure; and the second cooling system is arranged inside the throat brick.

Abstract: In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.

Abstract: Provided is an apparatus for improving reliability of a thermocouple in a cooling section of a channel during a heating stage. The apparatus includes a thermocouple and at least one thermocouple sheet installed on a cooling tube body. Each of the at least one thermocouple sheet is provided with a notch, and the notch has a groove structure. A cavity is formed between the notch and the cooling tube body, and a root of the thermocouple is disposed in the cavity. The root of the thermocouple is a temperature measuring point of a welded thermocouple.

Abstract: Methods, systems, and devices for shared parity storage are described. A memory system may include a shared parity storage configured to store parity information from multiple logical partitions of the memory system. For example, parity information associated with a first page of a first logical partition may be combined with parity information associated with a second page of a second logical partition, and stored to the shared parity storage. The memory system may support replacing combined parity information by deconstructing the combined parity information and reconstructing the combined parity information with parity information associated with another page of the first or second logical partition.

Abstract: The present disclosure relates to a method, apparatus, device, storage medium and program product for processing multimedia data. The method comprises: acquiring first multimedia draft data, wherein the first multimedia draft data is generated based on a segmented recording operation, video materials collected by the segmented recording operation being used to form video track segments in the first multimedia draft data; importing the first multimedia draft data into a first editor, so that the video track segments are displayed on a video editing track of the first editor; updating the first multimedia draft data in response to triggering a video editing operation for the video track segments on the first editor, to obtain second multimedia draft data; and generating a target video based on the second multimedia draft data in response to a trigger operation of video synthesis.

Abstract: Disclosed herein are an agitation structure and an agitation method. The agitation structure includes an agitation inlet pipe and an agitation tank. The agitation tank includes a buffer pool and an agitation container. The agitation container is communicably installed below the buffer pool. The agitation inlet pipe is communicably installed on a side wall of the buffer pool. The agitation tank is provided with an agitator.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to dynamically allocate blocks from a free block pool. The controller generates a free block pool that includes a collection of full blocks and a collection of partial good blocks (PGBs) of a set of memory components, a size of a full block in the collection of full blocks corresponding to a combination of two or more PGBs of the collection of PGBs. The controller receives a request to write data. The controller allocates an individual full block from the collection of full blocks or an individual PGB from the collection of PGBs based on determining whether the request to write the data has been received from the host device or the controller of the memory sub-system.

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a program-erase cycle count associated with at least a portion of the plurality of memory cells. The processing device is further to erase, based on the value of the PEC count, less than a predetermined portion of free sets of memory cells to form an erased set of memory cells. The processing device is further to receive a programming command directed to at least a portion of the erased set of memory cells. The processing device is further to perform a programming operation with respect to the at least a portion of the erased set of memory cells.

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

Abstract: Methods, systems, and devices for cross-temperature range management in memory systems are described. One or more parameter values defining an expected temperature range may be indicated to and stored at a memory system, where the memory system may define a safe temperature range and one or more additional temperature ranges using the one or more parameter values. After entering the safe temperature range, the memory system may refresh one or more memory cells of one or more memory devices for which write operations were performed outside of the safe temperature range. By defining safe temperatures for operation using an expected operating range, the memory system may reduce a quantity and frequency of refresh operations and may increase a performance and quality of service (QOS), while reducing latency in operations and communications. Further, endurance and device lifetime may be increased by reducing a quantity of refresh operations.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having first subset of word line groups (WGRs) that are categorized as being non-defective. The controller searches for a second PGB in the set of memory components having a second subset of WGRs that are categorized as being non-defective. The controller computes a total quantity of WGRs based on the first quantity of WGRs in the first subset of WGRs and a second quantity of WGRs in the second subset of WGRs and, in response, combines the first PGB and the second PGB to form an individual virtual block.

Abstract: Methods, systems, and devices for reducing read disturbance overestimation are described. A memory system may maintain a bitmap associated with a virtual block, where the virtual block may be associated with first blocks across multiple dies and each bit of the bitmap may correspond to a respective first block of each die. The memory system may perform a first read operation at the first block of a first die and, accordingly, may set a first bit of the bitmap to a first value. The memory system may determine whether to adjust a read counter associated with the virtual block based on values within the bitmap. For example, the memory system may adjust the read counter based on determining that each bit of the bitmap is set to the first value or based on performing a second read operation on the first block of the first die.