Abstract: A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance.

Abstract: A symbol rate estimation device includes: a power spectrum density (PSD) generating unit, estimating a power of an input signal to generate a PSD; a cut-off frequency index outputting unit, outputting a cut-off frequency index according to the power; and a symbol rate calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.

Abstract: A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal.

Abstract: A symbol rate estimating device includes: a power spectrum density (PSD) estimating unit, estimating a PSD of an input signal; an index searching unit, searching for a cut-off frequency index in the PSD; an adjacent channel interference (ACI) detecting unit, detecting whether the input signal has ACI to generate a detection signal; a threshold adjusting unit, generating an adjusted index number threshold according to the detection signal; an index output unit, outputting the cut-off frequency index according to the adjusted index number threshold; and a symbol calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.

Abstract: A symbol rate estimating device includes: a power spectrum density (PSD) estimating unit, estimating a PSD of an input signal; an index searching unit, searching for a cut-off frequency index in the PSD; an adjacent channel interference (ACI) detecting unit, detecting whether the input signal has ACI to generate a detection signal; a threshold adjusting unit, generating an adjusted index number threshold according to the detection signal; an index output unit, outputting the cut-off frequency index according to the adjusted index number threshold; and a symbol calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.

Abstract: A phase error detection module includes: a constellation point selector, generating a constellation point selection signal according to a position and a radius of data of an input signal in a constellation diagram; a symbol estimator, selecting a part of all of a plurality of constellation points in the constellation diagram according to the constellation point selection signal, as a plurality of reference constellation points for calculating an estimated symbol corresponding to the data of the input signal, and a quantity of the reference constellation points is smaller than a quantity of all of the constellation points of the constellation diagram; and a phase estimator, calculating an estimated phase error of the input signal according to the data of the input signal and the estimated symbol.

Abstract: A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal.

Abstract: A phase compensation method applied to a phase-locked loop (PLL) module of a communication device includes determining to output one of a maximum likelihood (ML) phase to an oscillator of the PLL module and a data-aided (DA) phase error to a filter of the PLL module according to an input signal. The ML phase is a phase generated from estimating known data in the input signal by using a ML method, and the DA phase error is a phase error generate from estimating the known data in the input signal by using a DA method.

Abstract: A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.

Abstract: A phase calibration method for a phase locked loop (PLL) circuit in a wireless communication device includes: calculating a header phase error of a header sub-frame of a frame in an input signal and a pilot phase error of a pilot sub-frame of the frame, wherein the header sub-frame and the pilot sub-frame are known data; generating an estimated phase error according to a relationship between the header phase error and the pilot phase error; generating a phase compensating signal according to the estimated phase error and a filtered signal; adjusting the input signal according to the phase compensating signal to generate a compensated input signal; detecting a phase error between a data sub-frame corresponding to the pilot sub-frame in the compensated input signal and a reference signal; and generating the filtered signal according to the phase error.

Abstract: A bandwidth adjustment method includes obtaining an upper bandwidth limit and a lower bandwidth limit according to an initial upper bandwidth limit and an initial lower bandwidth limit, obtaining an optimum bandwidth according to the upper bandwidth limit and the lower bandwidth limit, and adjusting the initial upper bandwidth limit and the initial lower and width limit according to the optimum bandwidth.

Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

Abstract: A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.

Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.