Abstract: A high-voltage metal-oxide-semiconductor (HVMOS) device and methods for forming the same are provided. The HVMOS device includes a substrate; a first high-voltage n-well (HVNW) region buried in the substrate; a p-type buried layer (PBL) horizontally adjoining the first HVNW region; a second HVNW region on the first HVNW region; a high-voltage p-well (HVPW) region over the PBL; an insulating region at a top surface of the second HVNW region; a gate dielectric extending from over the HVPW region to over the second HVNW region, wherein the gate dielectric has a portion over the insulating region; and a gate electrode on the gate dielectric.

Abstract: A high-voltage transistor device has a first well region with a first conductivity type in a semiconductor substrate, and a second well region with a second conductivity type in the semiconductor substrate substantially adjacent to the first well region. A field ring with the second conductivity type is formed on a portion of the first well region, and the top surface of the field ring has at least one curved recess. A field dielectric region is formed on the field ring and extends to a portion of the first well region. A gate structure is formed over a portion of the field dielectric region and extends to a portion of the second well region.

Abstract: A high-voltage metal-oxide-semiconductor (HVMOS) device and methods for forming the same are provided. The HVMOS device includes a substrate; a first high-voltage n-well (HVNW) region buried in the substrate; a p-type buried layer (PBL) horizontally adjoining the first HVNW region; a second HVNW region on the first HVNW region; a high-voltage p-well (HVPW) region over the PBL; an insulating region at a top surface of the second HVNW region; a gate dielectric extending from over the HVPW region to over the second HVNW region, wherein the gate dielectric has a portion over the insulating region; and a gate electrode on the gate dielectric.

Abstract: A high-voltage transistor device has a first well region with a first conductivity type in a semiconductor substrate, and a second well region with a second conductivity type in the semiconductor substrate substantially adjacent to the first well region. A field ring with the second conductivity type is formed on a portion of the first well region, and the top surface of the field ring has at least one curved recess. A field dielectric region is formed on the field ring and extends to a portion of the first well region. A gate structure is formed over a portion of the field dielectric region and extends to a portion of the second well region.

Abstract: A method of driving-in antimony into a wafer, including the following steps. A wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence of only a first nitrogen gas flow rate. The wafer is ramped-down from the first temperature to a second temperature in the presence of only an oxygen gas flow rate. The wafer is maintained in the presence of the of oxygen gas flow rate at the second temperature. The wafer is ramped-up from the second temperature to a third temperature in the presence of only the oxygen gas flow rate. The wafer is annealed a second time at the third temperature in the presence of only a second nitrogen gas flow rate to drive-in the antimony ions within the area of implanted antimony.