Patents by Inventor Ting Peng
Ting Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162150Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor; forming a plurality of first metal strips above the plurality of gate strips; and forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view; wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.Type: ApplicationFiled: January 25, 2024Publication date: May 16, 2024Inventors: SHIH-WEI PENG, HUI-TING YANG, WEI-CHENG LIN, JIANN-TYNG TZENG
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Publication number: 20240161293Abstract: A multi-label classification method for generating labels annotated on medical images. An initial dataset including medical images and partial input labels is obtained. The partial input labels annotate a labeled part of abnormal features on the medical images. A first multi-label classification model is trained with the initial dataset. Difficulty levels of the medical images in the initial dataset are estimated based on predictions generated by the first multi-label classification model. The initial dataset is divided based on the difficulty levels of the medical images into different subsets. A second multi-label classification model is trained based on subsets with gradually increasing difficulty levels during different curriculum learning rounds. Predicted labels annotated on the medical images are generated about each of the abnormal features based on the second multi-label classification model.Type: ApplicationFiled: November 16, 2023Publication date: May 16, 2024Inventors: Zhe-Ting LIAO, Yu-Shao PENG
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Patent number: 11981811Abstract: Provided are a use of a thermoplastic polyurethane for forming an impact resistant layer and an impact resistant composite laminate. The thermoplastic polyurethane comprises a structural unit represented by Formula (I): wherein each R independently is an alkylene group having 2 to 8 carbon atoms or CH2CH2OCH2CH2; n is a number from 2 to 13; and the structural unit has a Mn ranging from 700 g/mole to 2500 g/mole. In addition, the impact resistant layer has a thickness of larger than 1.5 mm. The impact resistant composite laminate comprises a base layer and the impact resistant layer disposed on the base layer.Type: GrantFiled: March 8, 2022Date of Patent: May 14, 2024Assignee: SUNKO INK CO., LTD.Inventors: Chiu-Peng Tsou, Zhen-Wei Chen, Ting-Ti Huang, Sheng-Mao Tseng
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Patent number: 11985906Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.Type: GrantFiled: March 12, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
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Publication number: 20240145579Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Yun PENG, Fu-Ting YEN, Keng-Chu LIN
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Publication number: 20240136438Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.Type: ApplicationFiled: December 22, 2023Publication date: April 25, 2024Inventors: Yu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
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Publication number: 20240132572Abstract: A fusion protein is disclosed. The fusion protein of the invention comprises an Fc fragment of an immunoglobulin G and a bioactive molecule, wherein the Fc is a single chain Fc. The amino acids in the hinge of the Fc is mutated, substituted, or deleted so that the hinge of Fc cannot form disulfide bonds. Methods for producing and using the fusion protein of the invention are also provided.Type: ApplicationFiled: September 25, 2023Publication date: April 25, 2024Inventors: Chang-Yi Wang, Wen-Jiun Peng, Wei-Ting Kao
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Patent number: 11968908Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.Type: GrantFiled: June 30, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
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Publication number: 20240129167Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.Type: ApplicationFiled: September 18, 2023Publication date: April 18, 2024Applicant: MEDIATEK INC.Inventors: Chung-Hsien Tsai, Che-Yu Chiang, Yu-Ting Liu, Tsung-Lin Lee, Chia-Sheng Peng, Ting-Ming Yang
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Publication number: 20240120376Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first active region extending lengthwise along a first direction and having a first width along a second direction perpendicular to the first direction, a second active region extending lengthwise along the first direction and having a second width along the second direction, and an epitaxial feature sandwiched between the first active region and the second active region along the first direction. The first width is greater than the second width.Type: ApplicationFiled: January 26, 2023Publication date: April 11, 2024Inventors: Po Shao Lin, Jiun-Ming Kuo, Yuan-Ching Peng, You-Ting Lin, Yu Mei Jian
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Publication number: 20240120932Abstract: Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight.Type: ApplicationFiled: December 3, 2023Publication date: April 11, 2024Applicant: Chongqing GigaChip Technology Co., Ltd.Inventors: Yabo NI, Yong ZHANG, Xiaofeng SHEN, Ting LI, Lu LIU, Can ZHU, Jiahao PENG, Liang LI, Dongbing FU, Jianan WANG
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Publication number: 20240104746Abstract: The present invention discloses a vessel tracking and monitoring system and operating method thereof. Specifically, the vessel tracking and monitoring system comprises at least one camera, a processing module and a storage module. On the other hand, the processing module may keep the water object which is detected and recognized by the at least one camera in the center area of a monitoring screen. Therefore, the present invention may track and recognize the type of the at least one water object, assisting areas such as ports in managing and tracking water object arrivals and departures under various environmental conditions.Type: ApplicationFiled: December 15, 2022Publication date: March 28, 2024Inventors: CHIA-YU WU, YAN-SHENG SONG, YU-TING PENG, CHIEN-HUNG LIU
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Patent number: 11942447Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.Type: GrantFiled: August 27, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: De-Yang Chiou, Fu-Ting Yen, Yu-Yun Peng, Keng-Chu Lin
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Patent number: 11944017Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.Type: GrantFiled: May 5, 2023Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20240098492Abstract: During operation, an access point may provide a first WLAN and a second WLAN, where the first WLAN uses a WPA2-compatible authentication protocol and the second WLAN uses a WPA3-compatible authentication protocol. In response to an association request or a probe request associated with (or from) an electronic device, the access point may establish a connection with the electronic device using the first WLAN. Then, the access point may confirm, with a computer system, that a binding between a passphrase associated with the electronic device and the second WLAN exists. Alternatively, when the binding does not exist, the access point may establish the binding in the computer system. Next, the access point may perform a BSS transition of the electronic device from the first WLAN to the second WLAN.Type: ApplicationFiled: September 6, 2023Publication date: March 21, 2024Applicant: ARRIS Enterprises LLCInventors: Wei-Sheng Hsu, Yu-Ting Chang, Weichih Huang, Kuan-Hsun Peng, Weiguo Xie, Christopher Mohammed, Shannon Moyes Clark, Siddhartha Datta, David Burns
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Publication number: 20240091764Abstract: A combinable nucleic acid pre-processing apparatus includes a sample transfer chamber transferring a sample from a sampling tube to a nucleic acid extraction kit, a nucleic acid extraction chamber performing a nucleic acid extraction of the sample in the nucleic acid extraction kit for obtaining a nucleic acid extract, an assay setup chamber preparing reagents and transferring reagents and the nucleic acid extract to an assay plate, and at least two bridging modules respectively disposed between the sample transfer chamber and the nucleic acid extraction chamber and between the nucleic acid extraction chamber and the assay setup chamber. The sample transfer chamber, the nucleic acid extraction chamber and the assay setup chamber are separated and operated independently. Three chambers are connected through the bridging modules, so the nucleic acid extraction kit can be sequentially moved in the sample transfer chamber, the nucleic acid extraction chamber and the assay setup chamber.Type: ApplicationFiled: September 19, 2023Publication date: March 21, 2024Inventors: Chien-Ting Liu, Shih-Fang Peng, Song-Bin Huang, Guo-Wei Huang, Jen-Chih Tsai
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Publication number: 20240099150Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 11929360Abstract: A device includes an electrical circuit having a first set of circuit elements. The device further includes a first set of conductive pillars over a first side of a substrate. The device further includes a first conductive rail electrically connected to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail. The device further includes a first plurality of power pillars extending through the substrate, wherein each of the first plurality of power pillars is electrically connected to the first conductive rail.Type: GrantFiled: July 13, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chieh Yang, Chung-Ting Lu, Yung-Chow Peng
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Publication number: 20240077392Abstract: According to the present disclosure, a measuring method of liquid mixture purity includes steps as follows. A storage tank is provided, wherein the storage tank is configured for storing a liquid mixture including formic acid and water. A calculating unit is provided, wherein a plurality of formic acid purity values are saved in the calculating unit. A pressure-decreasing and heating step is performed by reducing a pressure of the storage tank and heating the storage tank. A measuring step is performed by measuring in the inner space of the storage tank to obtain a pressure value, and measuring the liquid mixture simultaneously to obtain a temperature value. A calculating step is performed by inputting the pressure value and the temperature value into the calculating unit, wherein the calculating unit outputs one of the formic acid purity values corresponding thereto.Type: ApplicationFiled: April 11, 2023Publication date: March 7, 2024Inventors: Kuo-Liang YEH, Ya-Ju CHANG, Jung-Kuei PENG, Sheng-Tang CHANG, Min-Wen WENG, Wen-Ting HUANG
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Patent number: 11920213Abstract: Disclosed is an incomplete extraction method for recycling batteries, which may include: introducing a pretreatment gas into a device loaded with a waste battery powder, and bringing a gas outlet into communication with absorption liquid A and absorption liquid B in order; raising the temperature and introducing the pretreatment gas; reducing the temperature and introducing a reaction gas; raising the temperature, introducing the reaction gas, and then introducing the pretreatment gas; and reducing the temperature, and turning off the pretreatment gas; adding an extractant to absorption liquid A, mixing the mixture, taking organic phase A, adding a stripping agent, and taking aqueous phase A; and adjusting the pH to acidity, then adding an extractant, taking organic phase B, adding a stripping agent to obtain a stock solution enriched in Li, Mn, Ni and Co.Type: GrantFiled: April 30, 2021Date of Patent: March 5, 2024Assignees: GUANGDONG BRUNP RECYCLING TECHNOLOGY CO., LTD., HUNAN BRUNP RECYCLING TECHNOLOGY CO., LTD., HUNAN BRUNP EV RECYCLING CO., LTD.Inventors: Haijun Yu, Ting Peng, Yinghao Xie, Xuemei Zhang