Patents by Inventor Ting Shih Ang

Ting Shih Ang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power-aware debugging
    Patent number: 8176453
    Abstract: A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: May 8, 2012
    Assignee: Springsoft USA, Inc.
    Inventors: Kai Yang, Tayung Liu, Furshing Tsai, Ting Shih Ang, Chih Neng Hsu, Jun Zhao
  • POWER-AWARE DEBUGGING
    Publication number: 20100192115
    Abstract: A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
    Type: Application
    Filed: September 11, 2009
    Publication date: July 29, 2010
    Applicant: SPRINGSOFT USA, INC.
    Inventors: Kai Yang, Tayung Liu, Furshing Tsai, Ting Shih Ang, Chih Neng Hsu