Abstract: A fingerprint sensor includes a first reference capacitor, a second reference capacitor, a first capacitor and a second capacitor. A first reference voltage is established across the first reference capacitor. The first reference voltage is depended on a touch event, a first reference capacitance of the first reference capacitor and a stray capacitance. The second reference capacitor has a first end and a second end, and is being configured to maintain a voltage difference between the first end and the second end, the voltage difference being a function of the first reference voltage. The first capacitor has a first capacitance and is coupled to the first end. The second capacitor has a second capacitance and is selectively coupled in parallel with the first capacitor. The ratio of the stray capacitance to the first reference capacitance equals the ratio of the second capacitance to the first capacitance.

Abstract: A finger detection device and method of a fingerprint recognition IC is disclosed. The device comprises sensing electrodes, a capacitive sensing layer, a signal processing circuit, a multiplexer module and a signal register. The sensing electrodes are defined as a fingerprint sensing zone. The capacitive sensing layer covers the sensing electrodes. The signal processing circuit is arranged below and electrically connected with the sensing electrodes. The multiplexer module defines a finger detection zone. The finger detection zone includes at least one of the sensing electrodes. The signal register is electrically connected with the signal processing circuit, receiving a detection signal generated by the finger detection zone and comparing the detection signal with a preset value. The finger detection device uses only a portion of the sensing electrodes to detect a finger approaching/contacting it to determine triggering or sleeping of the fingerprint recognition IC and thus reduces power consumption.

Abstract: The present disclosure provides a fingerprint sensor that comprises a first reference capacitor, a second reference capacitor, a first capacitor and a second capacitor. A first reference voltage is established across the first reference capacitor. The first reference voltage is a function of a capacitance detected in response to a touch event, a first reference capacitance of the first reference capacitor and a stray capacitance. The second reference capacitor has a first end and a second end, and is being configured to maintain a voltage difference between the first end and the second end, the voltage difference being a function of the first reference voltage. The first capacitor has a first capacitance and is coupled to the first end of the second reference capacitor. The second capacitor has a second capacitance and is selectively coupled in parallel with the first capacitor.

Abstract: A finger sensing structure for a capacitive fingerprint recognition IC is provided here. The structure comprises a finger sensing metal layer with fish bone shape. When fingers approach or touch the surface of the capacitive fingerprint recognition IC, capacitive sense is induced between the fingers and the metal patterned layer to wake up the IC. Before the fingers approach or touch the IC, the IC is hibernated; once the fingers are detected, the IC is woken up. The metal patterned layer can reduce energy consumption of the IC especially for portable fingerprint recognition IC.

Abstract: A finger detection device and method of a fingerprint recognition IC is disclosed. The device comprises sensing electrodes, a capacitive sensing layer, a signal processing circuit, a multiplexer module and a signal register. The sensing electrodes are defined as a fingerprint sensing zone. The capacitive sensing layer covers the sensing electrodes. The signal processing circuit is arranged below and electrically connected with the sensing electrodes. The multiplexer module defines a finger detection zone. The finger detection zone includes at least one of the sensing electrodes. The signal register is electrically connected with the signal processing circuit, receiving a detection signal generated by the finger detection zone and comparing the detection signal with a preset value. The finger detection device uses only a portion of the sensing electrodes to detect a finger approaching/contacting it to determine triggering or sleeping of the fingerprint recognition IC and thus reduces power consumption.

Abstract: A finger sensing structure for a capacitive fingerprint recognition IC is provided here. The structure comprises a finger sensing metal layer with fish bone shape. When fingers approach or touch the surface of the capacitive fingerprint recognition IC, capacitive sense is induced between the fingers and the metal patterned layer to wake up the IC. Before the fingers approach or touch the IC, the IC is hibernated; once the fingers are detected, the IC is woken up. The metal patterned layer can reduce energy consumption of the IC especially for portable fingerprint recognition IC.

Abstract: A semiconductor device includes a substrate, a gate electrode, a pair of first impurity regions, a pair of second impurity regions and at least one dummy pattern. The gate electrode is positioned above the substrate. The first impurity regions are positioned in the substrate and near both sides of the gate electrode. The second impurity regions are positioned in the first impurity regions respectively, and the dopant concentration of the first impurity regions is lower than the dopant concentration of the second impurity regions. The dummy pattern is positioned over the first impurity regions and exposes the second impurity regions.

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer.

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract: The present invention provides an inline detection device for self-aligned contact defects, formed in a semiconductor substrate, comprising: an active area, formed in the semiconductor substrate, comprised of a serpentine gate having spacers on the side, a plurality of first contact windows nested immediately between the same spacers, a plurality of first contact plugs formed in the first contact windows, and two probing pads, formed in the semiconductor substrate, comprised of a plurality of matrix gates, a second contact window exposing portions of the matrix gates, and a second contact plug formed in the second contact window.

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

Abstract: The present invention provides an inline detection device for self-aligned contact defects, formed in a semiconductor substrate, comprising: an active area, formed in the semiconductor substrate, comprised of a first gate having spacers on the side, at least one contact window formed between the spacers, a first contact plug formed in the first contact window, and a first contact area connecting with the first contact plug; and at least two probing pads, formed in the semiconductor substrate, comprised of a plurality of second gates formed with spacers on the side, second contact windows exposing the second gates, a second contact plug formed in the second contact window, and a second contact area connecting with the first contact area. According to the present invention, defects are detected by electrical measurement immediately following the formation of contact plugs.

Abstract: A method of manufacturing a trench non-volatile memory cell, comprises the steps of: providing a semiconductor substrate; performing ion implantation to form a source region in the semiconductor substrate; forming a trench on the semiconductor substrate by silicon etching, the trench reaching down to the source region; growing a first isolation layer on the surface of the semiconductor substrate, and the bottom and sidewall of the trench; forming a hollow-shaped first conducting layer in the trench; performing thermal oxidation on the first conducting layer to form a bird's beak isolation layer and a floating gate, which are the oxidized and unoxidized part of the first conducting layer, respectively, wherein the floating gate has a peak; partially removing the first isolation layer and the bird's beak isolation layer to bare the surface of the semiconductor substrate, the peak and the sidewall of the trench; depositing a second conducting layer; patterning the second conducting layer to form a cont

Abstract: The present invention provides a new method for making a load resistor in a semiconductor chip. According to the new method, a linear-shaped doped polysilicon layer is formed onto the surface of the semiconductor chip that comprises a Si substrate and an NSG layer. This layer functions as a conductive path. A slot is formed in this layer by removing a section from the conductive path. This slot reaches down to the NSG layer effectively cutting off the polysilicon layer. Then, a rugged polysilicon layer is evenly deposited onto the surface of the slot for connection of the conductive path. The polysilicon layer over the slot and the doped polysilicon layer defines the load resistor. The result is a high resistance value with usage of only a small space.

Abstract: The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer with a fluorine-containing gas by which a fluorine-containing layer is formed on a surface of said bonding pad structure; and b) removing the fluorine-containing layer for reducing a contact resistance of said bonding pad structure.

Abstract: A TFT LCD device is comprised of four TFT's with two separate sources, two separate drains and one common source-drain which is shared by the four respective TFT's, either acting as source or drain. The gate structure employs only one gate line with a bypass line. By sharing of the Si island and the centralization of the gate electrode of four TFT's, the pixel open ratio increases quite substantially. The devices are connected to the two adjacent pixels separated by the gate line via the two drain electrodes. Each pixel electrode is connected to the two adjacent devices via the two drain electrodes. Each pixel electrode can receive the data signals which are controlled by the two adjacent devices, to form a redundant structure for improving the yield of the TFT LCD. The common source-drain is situated along the gate bus line, and doesn't occupy too much of the pixel area, to thereby provide a large open ratio.