Abstract: A fingerprint sensor includes a first reference capacitor, a second reference capacitor, a first capacitor and a second capacitor. A first reference voltage is established across the first reference capacitor. The first reference voltage is depended on a touch event, a first reference capacitance of the first reference capacitor and a stray capacitance. The second reference capacitor has a first end and a second end, and is being configured to maintain a voltage difference between the first end and the second end, the voltage difference being a function of the first reference voltage. The first capacitor has a first capacitance and is coupled to the first end. The second capacitor has a second capacitance and is selectively coupled in parallel with the first capacitor. The ratio of the stray capacitance to the first reference capacitance equals the ratio of the second capacitance to the first capacitance.

Abstract: A finger detection device and method of a fingerprint recognition IC is disclosed. The device comprises sensing electrodes, a capacitive sensing layer, a signal processing circuit, a multiplexer module and a signal register. The sensing electrodes are defined as a fingerprint sensing zone. The capacitive sensing layer covers the sensing electrodes. The signal processing circuit is arranged below and electrically connected with the sensing electrodes. The multiplexer module defines a finger detection zone. The finger detection zone includes at least one of the sensing electrodes. The signal register is electrically connected with the signal processing circuit, receiving a detection signal generated by the finger detection zone and comparing the detection signal with a preset value. The finger detection device uses only a portion of the sensing electrodes to detect a finger approaching/contacting it to determine triggering or sleeping of the fingerprint recognition IC and thus reduces power consumption.

Abstract: The present disclosure provides a fingerprint sensor that comprises a first reference capacitor, a second reference capacitor, a first capacitor and a second capacitor. A first reference voltage is established across the first reference capacitor. The first reference voltage is a function of a capacitance detected in response to a touch event, a first reference capacitance of the first reference capacitor and a stray capacitance. The second reference capacitor has a first end and a second end, and is being configured to maintain a voltage difference between the first end and the second end, the voltage difference being a function of the first reference voltage. The first capacitor has a first capacitance and is coupled to the first end of the second reference capacitor. The second capacitor has a second capacitance and is selectively coupled in parallel with the first capacitor.

Abstract: A finger sensing structure for a capacitive fingerprint recognition IC is provided here. The structure comprises a finger sensing metal layer with fish bone shape. When fingers approach or touch the surface of the capacitive fingerprint recognition IC, capacitive sense is induced between the fingers and the metal patterned layer to wake up the IC. Before the fingers approach or touch the IC, the IC is hibernated; once the fingers are detected, the IC is woken up. The metal patterned layer can reduce energy consumption of the IC especially for portable fingerprint recognition IC.

Abstract: A finger detection device and method of a fingerprint recognition IC is disclosed. The device comprises sensing electrodes, a capacitive sensing layer, a signal processing circuit, a multiplexer module and a signal register. The sensing electrodes are defined as a fingerprint sensing zone. The capacitive sensing layer covers the sensing electrodes. The signal processing circuit is arranged below and electrically connected with the sensing electrodes. The multiplexer module defines a finger detection zone. The finger detection zone includes at least one of the sensing electrodes. The signal register is electrically connected with the signal processing circuit, receiving a detection signal generated by the finger detection zone and comparing the detection signal with a preset value. The finger detection device uses only a portion of the sensing electrodes to detect a finger approaching/contacting it to determine triggering or sleeping of the fingerprint recognition IC and thus reduces power consumption.

Abstract: A finger sensing structure for a capacitive fingerprint recognition IC is provided here. The structure comprises a finger sensing metal layer with fish bone shape. When fingers approach or touch the surface of the capacitive fingerprint recognition IC, capacitive sense is induced between the fingers and the metal patterned layer to wake up the IC. Before the fingers approach or touch the IC, the IC is hibernated; once the fingers are detected, the IC is woken up. The metal patterned layer can reduce energy consumption of the IC especially for portable fingerprint recognition IC.

Abstract: A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

Abstract: A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide layer on one step surface can be different from that on another step surface of the multi-step structure. In addition, the recessed gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure, and these doped regions may use different dosages and different types of dopants. There is a carrier channel in the semiconductor substrate under the recessed gate structure and the overall channel length of the carrier channel is substantially the summation of the lateral width and twice of the vertical depth of the recessed gate structure.

Abstract: A method for preparing a dynamic random access memory structure, comprising steps of forming a bottom conductive region in a substrate, removing a predetermined portion of the substrate to form a plurality of pillars having a bottom end lower than a bottom surface of the bottom conductive region, forming a first oxide layer on the substrate and below the bottom conductive region in the pillar, forming a conductive block between two adjacent pillars to electrically connect the two bottom conductive regions in the two adjacent pillars, forming a second oxide layer covering the conductive block, forming a gate oxide layer on a sidewall of the pillar, forming a gate structure on a surface of the gate oxide layer; and forming an upper conductive region on a top portion of the pillar.

Abstract: A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively.

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract: A semiconductor device includes a substrate, a gate electrode, a pair of first impurity regions, a pair of second impurity regions and at least one dummy pattern. The gate electrode is positioned above the substrate. The first impurity regions are positioned in the substrate and near both sides of the gate electrode. The second impurity regions are positioned in the first impurity regions respectively, and the dopant concentration of the first impurity regions is lower than the dopant concentration of the second impurity regions. The dummy pattern is positioned over the first impurity regions and exposes the second impurity regions.

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer.

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract: The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

Abstract: The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

Abstract: The present invention provides an inline detection device for self-aligned contact defects, formed in a semiconductor substrate, comprising: an active area, formed in the semiconductor substrate, comprised of a serpentine gate having spacers on the side, a plurality of first contact windows nested immediately between the same spacers, a plurality of first contact plugs formed in the first contact windows, and two probing pads, formed in the semiconductor substrate, comprised of a plurality of matrix gates, a second contact window exposing portions of the matrix gates, and a second contact plug formed in the second contact window.

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.