Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.

Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.

Abstract: A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.

Abstract: A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.

Abstract: The present invention discloses a method for crosstalk elimination in high-performance processors. The method, based on the combination of a deassembler and an assembler, eliminates crosstalk with fewer extra wires. The method of the present invention includes the steps of: deassembling a first piece of data to a plurality of data segments; conducting a parallel crosstalk check on the data segments to form a second piece of data that is crosstalk-free; and restoring the first piece of data based on the second piece of data. The present invention also discloses a bus architecture performing the method for crosstalk elimination, which includes a deassembler, a transmission bus and an assembler.