Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple wall. The control gate is negatively biased. By biasing the P-well and drain (or source) positively within a particular voltage range when erasing, GIDL current and degradation from a hole trapping can be diminished and hence scalable technology may be achieved.

Abstract: A nonvolatile memory cell is formed in an embedded P-well without the necessity of including an overlaying control gate. As a result, normal logic process technology may be utilized to form the nonvolatile memory cell. Through the use of substrate hot electron injection and the formation of a lateral bipolar transistor whose emitter acts as a charge injector, programming efficiency is improved and the necessary programming voltages and currents can be reduced from the relatively high voltages and currents used in other devices.

Abstract: A nonvolatile memory cell is formed in an embedded P-well without the necessity of including an overlaying control gate. As a result, normal logic process technology may be utilized to form the nonvolatile memory cell. Through the use of substrate hot electron injection and the formation of a lateral bipolar transistor whose emitter acts as a charge injector, programming efficiency is improved and the necessary programming voltages and currents can be reduced from the relatively high voltages and currents used in other devices.

Abstract: A nonvolatile memory cell is formed in an embedded P-well without the necessity of including an overlaying control gate. As a result, normal logic process technology may be utilized to form the nonvolatile memory cell. Through the use of substrate hot electron injection and the formation of a lateral bipolar transistor whose emitter acts as a charge injector, programming efficiency is improved and the necessary programming voltages and currents can be reduced from the relatively high voltages and currents used in other devices.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

Abstract: A high performance programmable interconnect enables scaled transistors to be utilized, in conjunction with memory cells, as transfer gates with improved speed characteristics. Boosted positive and negative drive voltages are supplied to the transfer gate depending on the programmed state of the memory cell. The transfer gate may be driven by an inverter using a transistor formed in a triple well.

Abstract: A buried contact module is provided that includes a dopant-diffusion buffer layer. The dopant-diffusion buffer layer is formed with a thin dielectric region fabricated between the polysilicon contact region and the well region. The dielectric region formed of, for example, silicon dioxide, limits the amount of phosphorous diffusion into the well region. Thus, a buried contact junction can be formed in an integrated circuit having a high punch-through voltage characteristic, a low junction leakage current characteristic and a low polysilicon resistance. In addition, the buried contact junction maintains a relatively low buried contact resistance.

Abstract: A control circuit for erasing EEPROM memory cells is disclosed, including a charge pump having two switched constant current sources driven by opposing clocks. Current produced by the current sources is coupled to a node from where it is used to erase EEPROM memory cells. A switch is provided to isolate the device being erased by floating its source.

Abstract: An electrically programmable, electrically erasable semiconductor memory apparatus for storing information in which the equivalent of a floating gate memory device and a select transistor device are combined in a single device cell is disclosed. A single control gate both controls a select transistor and is used in programming the floating gate.