Patents by Inventor Ting Wei

Ting Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210015377
    Abstract: A device, method and system for calculating, estimating, or monitoring the blood pressure of a subject. A first signal representing heart activity of a subject may be received. A plurality of second signals representing time-varying information on at least one pulse wave of the subject may be received from a plurality of body locations of the subject. A first feature of the first signal may be identified. For each of the plurality of second signals, a second feature may be identified. A pulse transit time based on a difference of the first feature and at least one of the second features may be computed. A blood pressure of the subject may be calculated according to a model based on the computed pulse transit time. The model may include a compensation term relating to the plurality of second signals or the second features thereof.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: VITA-COURSE TECHNOLOGIES CO., LTD.
    Inventors: Chuanmin WEI, Ting MA, Jiao YU, Zhiyong WANG, Jiwei ZHAO
  • Patent number: 10896004
    Abstract: High-efficiency control technology for non-volatile memory. A controller allocates spare blocks of a non-volatile memory to provide an active block and writes data issued by a host to the active block. The controller further uses the active block as the destination for data transferred from a first source block when there are fewer spare blocks than the threshold amount. When a second source block meets the transfer requirements, the controller uses the active block as the destination for data transferred from the second source block.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 19, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Ting-Han Lin, Che-Wei Hsu
  • Publication number: 20210014702
    Abstract: A data communication system able to provide a speedy response to a user equipment transmitting data includes a base station and a data center. The base station is disposed adjacent to the data center, the base station is coupled between the data center and the user equipment, and the base station transmits data provided by the user equipment to the data center. The data center processes first data from the user equipment, and transmits a second data to the user equipment through the base station. Therefore, the data transmission time between the data center and the user equipment is shortened, and the data can be quickly fed back to the user equipment.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: YAO-TING CHANG, CHAO-KE WEI, TZE-CHERN MAO, LI-WEN CHANG, HUI-HSUAN WANG
  • Publication number: 20210013395
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.
    Type: Application
    Filed: August 1, 2019
    Publication date: January 14, 2021
    Inventors: Chih-Wei Kuo, Ting-Hsiang Huang, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10890429
    Abstract: An automatic calibration optical interferometer comprises: a light source; an optical interference assembly, which divides a low coherent light into a first and a second incident light; an optical sampling assembly, with a first end receiving the first incident light and a partially reflective window at the second end being configured to divide the first incident light into a first reflected light and a first penetrating light configured to be emitted to the test sample; an optical reference assembly, with a reference mirror and an actuator, wherein the optical sampling assembly emits the second incident light to the reference mirror to generate a second reflected light, and the actuator moves the reference mirror; a polychromator, which outputs a displacement signal according to an optical path difference variation between the first and second reflected lights; and a displacement controller, which controls the actuator according to the displacement signal.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 12, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hung Chih Chiang, Cheng Yi Chang, Ting Wei Chang, Chi Shen Chang
  • Publication number: 20210004518
    Abstract: A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Kuang-Ching CHANG, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Jung-Chan YANG
  • Patent number: 10887929
    Abstract: The present disclosure provides a resource allocation method. The resource allocation method includes the following steps: selecting multiple first selected virtual nodes according to multiple virtual pheromonal trails on multiple virtual edges, in which the first selected virtual nodes forms at least one virtual tour, and the virtual tour includes multiple first virtual edges; updating the virtual pheromonal trails on the virtual edges according to virtual distances corresponding to the first virtual edges of the virtual tour; selecting multiple second selected virtual nodes according to the updated virtual pheromonal trails on the virtual edges, in which the second selected virtual nodes form at least one resulting virtual tour; allocating the resource blocks to selected user pairs according to the resulting virtual tour.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: January 5, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ting-Wei Lai, Hsuan-Jung Su, Der-Zheng Liu
  • Patent number: 10885254
    Abstract: A method of manufacturing an integrated circuit includes manufacturing a first set of conductive features by a first mask, positioning a set of gates in a second direction, manufacturing a second set of conductive features by a second mask, and electrically coupling a first portion of the set of gates to a second portion of the set of gates. The first and second set of conductive features is in a first direction and a first layer. The set of gates is in a second layer. The first portion of the set of gates corresponds to a gate terminal of a first n-type transistor, the second portion of the set of gates corresponds to a gate terminal of a first p-type transistor, the first n-type transistor being part of a first transmission gate, and the first p-type transistor being part of a second transmission gate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien
  • Publication number: 20200411681
    Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20200411516
    Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.
    Type: Application
    Filed: June 9, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin-Dai SUE, Tzung-Yo HUNG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Publication number: 20200409899
    Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Joon Teik Hor, Ting Lok Song, Mahesh Wagh, Su Wei Lim
  • Publication number: 20200408508
    Abstract: A wireless charging device and an operation method thereof are provided. The wireless charging device includes a charging module, at least one proximity sensor and a central controller. The wireless charging device senses a distance variation between the wireless charging device and an object using the proximity sensor and accordingly determines whether to turn on or turn off the charging module to achieve energy saving.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: TING-YANG CHANG, SHIH-WEI KUO, YEN-MIN CHANG
  • Publication number: 20200409238
    Abstract: In accordance with some embodiments, a method of forming an auto-focusing device is provided. The method includes forming a cantilever beam member. The cantilever beam member has a ring shape. The method further includes forming a piezoelectric member over the cantilever beam member. The method also includes forming a membrane over the cantilever beam member. The membrane has a first region and a second region. The first region has a planar surface, and the second region is located between the first region and an inner edge of the cantilever beam member and has a plurality of corrugation structures. In addition, the method includes applying a liquid optical medium over the membrane and sealing the liquid optical medium with a protection layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Jung CHEN, Shih-Wei LIN
  • Patent number: 10879458
    Abstract: A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Patent number: 10878881
    Abstract: The memory apparatus includes a plurality of memory chips and a plurality of temperature sensors. The memory chips are coupled to each other. The temperature sensors are respectively disposed on the memory chips. One of the memory chips is configured to be a master memory chip, and a first temperature sensor of the master memory chip is enabled to sense an ambient temperature. The master memory chip generates a refresh rate control signal according to the ambient temperature and controls refresh rates of all of the memory chips.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10879135
    Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shang-Wei Fang, Jing-Sen Wang, Yuan-Yao Chang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee, Yu-Hsuan Huang
  • Publication number: 20200402948
    Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 24, 2020
    Inventors: TING-YING WU, CHIEN-HSIANG HUANG, CHIN-YUAN LO, CHIH-WEI CHANG
  • Publication number: 20200402979
    Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
    Type: Application
    Filed: May 20, 2020
    Publication date: December 24, 2020
    Inventors: Shao-Lun Chien, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue
  • Publication number: 20200394099
    Abstract: Mapping information management for data storage. A mapping information format without any uncorrectable flag bits (UNC bits) is shown. A controller provides a cyclic redundancy check (CRC) engine. In response to an uncorrectable marking command issued by a host, the controller operates the cyclic redundancy check engine to encode a data pattern with a biased encoding seed to generate biased cyclic redundancy check code. The controller programs the data pattern and the biased cyclic redundancy check code to the non-volatile memory. The data pattern, therefore, will not pass CRC. The uncorrectable marking command works.
    Type: Application
    Filed: January 28, 2020
    Publication date: December 17, 2020
    Inventors: Ting-Han LIN, Che-Wei HSU
  • Publication number: 20200394131
    Abstract: Mapping information management for data storage devices is provided. A controller caches write data issued by a host in a temporary storage and then programs the cached write data from the temporary storage to a non-volatile memory. The controller uses a mapping information format to manage mapping information of logical addresses recognized by the host. As presented in the mapping information format, the values not greater than a first threshold value and mapped to the configuration information storage space of the non-volatile memory are at least partially used to point to the temporary storage, and the values greater than the first threshold value are mapped to the non-volatile memory.
    Type: Application
    Filed: January 28, 2020
    Publication date: December 17, 2020
    Inventors: Ting-Han LIN, Che-Wei HSU