Patents by Inventor Ting-Wei CHIEN

Ting-Wei CHIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105726
    Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 28, 2024
    Inventors: Shao-Lun Chien, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue
  • Patent number: 11941410
    Abstract: Systems and methods for generating, distributing, and using performance mode BIOS configurations are disclosed. Each performance mode BIOS configuration can be a unique set of BIOS setting values that have been established to optimize a particular performance parameter or set of performance parameters, such as boot speed or operating system installation speed. Based on a given hardware configuration and/or set of performance parameters, one or more performance mode BIOS configurations can be packaged and transferred to a memory of a BMC in the form of one or more configuration payloads. The BIOS Setup Utility can display all configuration payloads, such as listed by the type of performance mode (e.g., “Boot Speed Performance Mode” and “OS Installation Performance Mode”), that are available in the BMC memory and allow a user to overwrite the memory containing the current BIOS configuration with a selected configuration payload.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: March 26, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Lung-Chih Chen, Tian-You Chen, Ting-Wei Chien, Chao-Kai Huang
  • Publication number: 20230229453
    Abstract: Systems and methods for generating, distributing, and using performance mode BIOS configurations are disclosed. Each performance mode BIOS configuration can be a unique set of BIOS setting values that have been established to optimize a particular performance parameter or set of performance parameters, such as boot speed or operating system installation speed. Based on a given hardware configuration and/or set of performance parameters, one or more performance mode BIOS configurations can be packaged and transferred to a memory of a BMC in the form of one or more configuration payloads. The BIOS Setup Utility can display all configuration payloads, such as listed by the type of performance mode (e.g., “Boot Speed Performance Mode” and “OS Installation Performance Mode”), that are available in the BMC memory and allow a user to overwrite the memory containing the current BIOS configuration with a selected configuration payload.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Inventors: Lung-Chih CHEN, Tian-You CHEN, Ting-Wei CHIEN, Chao-Kai HUANG