Patents by Inventor TING-WEI CHOU

TING-WEI CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11935888
    Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pin-Dai Sue, Ting-Wei Chiang, Hui-Zhong Zhuang, Ya-Chi Chou, Chi-Yu Lu
  • Publication number: 20240071833
    Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Huan Chen, Huan-Chih Yuan, Yu-Chang Jong, Scott Yeh, Fei-Yun Chen, Yi-Hao Chen, Ting-Wei Chou
  • Publication number: 20220044954
    Abstract: The present invention reveals an alignment platform for aligning electronic component precisely to the operation position during testing or hot pressing processes. The alignment platform makes a rotor to rotate by a driving apparatus. The rotor has an eccentric axle to where a connecting member is disposed. The connecting member is moved by the eccentric axle, driving an active plate to move. The eccentric axle, the driving apparatus, the connecting member, and the active plate are configured to move under control in a micro or nano meter scale. Thus, precisely alignment of electronic component can be achieved. Floating mechanism of electronic component transmission apparatus or electronic component handler may be dismissed for lowering cost and prolonging lifetime.
    Type: Application
    Filed: July 20, 2021
    Publication date: February 10, 2022
    Inventors: Yuan-Long Chang, Ting Wei Chou
  • Patent number: 9691750
    Abstract: In some embodiments, a semiconductor device comprises a first active region, a second active region, and a conductive metal structure. The second active region is separate from the first active region. The conductive metal structure is arranged to connect the first active region and the second active region. The conductive metal structure includes a first leg, a second leg and a body. The second leg is separate from the first leg and a body extending between and connecting the first leg and the second leg.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ting-Wei Chou, Wen-Lang Wu, Chitong Chen, Shun Li Chen, Ting-Wei Chiang, Li-Chun Tien
  • Publication number: 20160225752
    Abstract: In some embodiments, a semiconductor device comprises a first active region, a second active region, and a conductive metal structure. The second active region is separate from the first active region. The conductive metal structure is arranged to connect the first active region and the second active region. The conductive metal structure includes a first leg, a second leg and a body. The second leg is separate from the first leg and a body extending between and connecting the first leg and the second leg.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: TING-WEI CHOU, WEN-LANG WU, CHITONG CHEN, SHUN LI CHEN, TING-WEI CHIANG, LI-CHUN TIEN