Abstract: The present invention provides a method for preparing conductor material with large surface area, which comprises steps of: forming a block layer on the outer surface of a support precursor (for example, a conductive nanometer fiber) for producing a mixed precursor; rolling the mixed precursor to crack a portion of the outer surface of the block layer for producing a plurality of crack-gaps and exposing a portion of the outer surface of the support precursor from the plurality of crack-gaps; and adding a conductor material to the mixed precursor so that the conductor material contacts and is connected electrically to the support precursor via the plurality of crack-gaps for producing a conductor material with large surface area.

Abstract: A process for the preparation of a glass fiber reinforced composition containing a recycled polypropylene includes a) unwinding from a package the continuous glass multifilament strands, b) applying an impregnating agent to the continuous glass multifilament strands to form the impregnated continuous multifilament strands and c) applying the sheath of a first polymer composition around the impregnated continuous multifilament strands to form the sheathed continuous multifilament strands, d) pelletizing the sheathed continuous multifilament strands to form pellets of the sheathed multifilament strands, e) homogenizing the pellets of the sheathed multifilament strands with a second polymer composition, wherein the first polymer composition comprises at least 80 wt % of a recycled polypropylene (PP1), and the second polymer composition includes at least 80 wt % of a second polypropylene (PP2), wherein the MFI of the PP1 and PP2 satisfy the following equation: 0.2?MFIPP1/MFIPP2?1.2.

Abstract: A field effect transistor including a substrate; a monolayer of a single crystal semiconducting transition metal dichalcogenide (TMD) on the substrate; a source contact and a drain contact to the strained monolayer; and a gate contact on the substrate; wherein the a gate voltage applied to the gate contact with respect to the source contact modulates a ferroelectric response of the monolayer when strained and a current through the monolayer between the source contact and the drain contact; and wherein the substrate is rigid and the monolayer experiences asymmetric lattice expansion when strained against the rigid substrate in response to an external magnetic field or the substrate is a strain engineered substrate inducing asymmetric lattice expansion of the monolayer.

Abstract: Provided are compositions and methods of use of a pharmaceutical composition in the manufacture of a medicament for preventing or treating a diabetic kidney disease, the pharmaceutical composition including a chemokine C-C motif ligand 7 (CCL7) antagonist and/or a pharmaceutically acceptable salt thereof and a pharmaceutically acceptable carrier. The medicament can prevent or treat diabetic kidney disease by protecting tubular epithelial cells, reducing glomerular hypertrophy, glomerulosclerosis, and fibrosis. The present disclosure also provides a method for preventing or treating a diabetic kidney disease in a subject in need thereof, including administering an effective amount of a CCL7 antagonist and/or a pharmaceutically acceptable salt thereof to the subject to inhibit an activity of CCL7.

Abstract: A calibration apparatus for calibrating a transceiver includes a loop back circuit, an estimation circuit, and a calibration circuit. The loop back circuit is coupled between a mixer output port of a transmitter (Tx) of the transceiver and a mixer input port of a receiver (Rx) of the transceiver, and applies a sequence of different loop gains. The estimation circuit receives a loop back receiving signal that is output from the Rx under the sequence of different loop gains, and generates at least one estimated value of impairment of the transceiver by performing channel estimation according to at least the loop back receiving signal. The calibration circuit performs calibration upon the transceiver according to the at least one estimated value.

Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Abstract: The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.

Abstract: Self-tuning merged code testing is provided which includes testing merged code using a suite of test cases, where the merged code includes one or more code changes, and obtaining, based on the testing, a test case failure using the suite of test cases. Further, the process includes determining, using an artificial intelligence engine, a likely faulty code change of the one or more code changes resulting in the test case failure, and customizing, based on the likely faulty code change, the suite of test cases to facilitate verifying that the likely faulty code change is a faulty code change. In addition, the process includes continuing testing of the merged code using the customized suite of test cases to facilitate verifying that the likely faulty code change is the faulty code change.

Abstract: An extraction method of Hibiscus sabdariffa L. ‘TAITUNG NO. 6’, a Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ extract using the same, and uses thereof are provided. The extraction method includes: providing the Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ that is dried as a raw material for extraction; pulverizing the raw material; mixing the raw material that is pulverized with an extraction solvent for primary extraction, so as to obtain a Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ primary extract; performing ultrasonic extraction on the Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ primary extract, so as to obtain a Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ extract; and filtering the Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ extract.

Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.

Abstract: A touch sensor includes a resistive layer on a substrate and electrodes on the resistive layer. The electrodes and portions of the resistive layer between the electrodes form series resistor chains disposed at peripheral regions of the touch sensor and surrounding a touch region of the touch sensor. The electrodes are formed by forming a conductive layer on the resistive layer in a thin-film deposition process, followed by patterning the conductive layer into the electrodes. A sheet resistivity of the resistive layer is between about 200? and about 800?. A sheet resistivity of the conductive layer is between about 0.03? and about 0.2?. A ratio of the sheet resistivity of the resistive layer to the sheet resistivity of the conductive layer is between about 2,500 and about 10,000.

Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: Provided is an injectable sustained release pharmaceutical formulation, including 3-acyl-naltrexone or a pharmaceutically acceptable salt thereof, a biocompatible organic solvent, and optionally a biocompatible polymeric material. Also provided is a method for treating opioid use disorder or alcoholism, including administering the injectable sustained release pharmaceutical formulation to a subject in need thereof. The pharmaceutical formulation provides a sustained release profile after one single injection, and the plasma levels of naltrexone in minipigs could provide a sustained release for 2 months.

Abstract: A method for obtaining regenerated seedlings of Brassica campestris L. ssp. chinensis from embryonic tip tissues, including the following steps. A seed is inoculated to a germination medium for dark culture for 60 h. The testa, root tip, two cotyledons and middle growing point of the resultant germinated seed are removed, and an embryonic tip with a length of 3-5 mm is retained as an explant. The explant is sequentially subjected to low-temperature pre-culture in a pre-culture medium for 36 h, room-temperature shaking culture in a liquid bud induction culture medium for 10 min, and bud induction culture in a bud induction culture medium for 20 d. A regenerated plant with 5-6 leaves is transferred to a rooting medium for rooting culture for about 2 weeks, and a well-rooted plant is collected, and subjected to hardening and transplantation into a filed.

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.

Abstract: A tape measure comprises a housing containing a tape, spring, reel, and hub, with first seal(s) to seal between the reel cartridge and the hub and/or to seal between the reel and the housing and/or a part fixed to the housing. An outermost coil of the spring may extend out of an opening in the reel and be attached to an innermost coil of the tape, and a second seal may be provided on the reel, to seal between the spring and the reel where the spring extends from the reel. Alternatively, the spring may be contained within the reel, and an outermost coil of the spring may be attached to an interior of the reel. An exterior of the reel may include an attachment portion to which an innermost coil of the tape is attached. The housing may be openable to enable contaminants to be removed from the housing.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.

Abstract: A method includes providing a semiconductor structure including a fin protruding from a substrate, where the fin includes first semiconductor layers and second semiconductor layers, recessing the fin to form a source/drain (S/D) recess, forming an S/D feature in the S/D recess, trimming the S/D feature, depositing a dielectric layer to cover the S/D feature, forming a contact hole in the dielectric layer to expose the S/D feature, and forming a metal contact in the contact hole.