Abstract: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract: A nanoindentation apparatus is used to measure adhesion strength of a hard, thin film to a soft substrate. A variably increasing load is applied to the indenter tip. The indenter tip penetrates into the thin film at a first penetration rate and causes the thin film to sink into the substrate thus causing a tensile stress at the film substrate interface. At a critical value of the applied load, the stress at the interface exceeds the delamination value, and the thin film partially delaminates from the substrate. This causes the indenter tip to sink into the softer substrate at a sudden second, higher penetration rate. A sensor detects the applied load and the indenter tip penetration depth at this point. A computer flags the critical value of the applied load that corresponds to the increased penetration depth rate at the point of delamination of the film.

Abstract: A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.

Abstract: There is provided a new polysilicon fuse structure for implementation within integrated circuit devices so as to permit programming of the same. The polysilicon fuse structure includes a first electrical contact region, a second electrical contact region, and multiple fuse regions interconnected between the first electrical contact region and the second electrical contact region. The multiple fuse regions are formed of a plurality of strips, each being of a different width and/or length, which are disposed in a spaced-apart relationship so as to form a small opening between adjacent strips. A number of the plurality of strips is selectively blown when a predetermined amount of current is passed from one of the first and second electrical contact regions through the plurality of strips to the other one of the first and second electrical contact regions so to limit the current passing to an integrated circuit device connected thereto during normal operating conditions.

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract: A nanoindentation apparatus is used to measure the in-plane fracture toughness of a thin film formed on a substrate. One or more notches are formed in the thin film. An indenter is applied to the thin film near the notch or notches and a load is applied to the indenter to force it into the thin film. Because the substrate is softer than the thin film, the indenter does not penetrate the thin film, but "sinks in" to the soft substrate. The sink in effect enhances the tensile strain and stress at the notch. In one embodiment, both the penetration of the indenter into the thin film and substrate and the load on the indenter are measured. When the thin film fractures at the notch or notches, the indenter sharply sinks into the substrate. The thin film fracture toughness is then calculated based on the value of the load and penetration at the point of fracture using either finite element analysis or an analytical model.