Patents by Inventor Ting-Yang Wang

Ting-Yang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224739
    Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: February 11, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yueh-Min Chen, Ting-Yang Wang, Yu-Hsin Lin, Wen-Chieh Wang
  • Publication number: 20230396246
    Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.
    Type: Application
    Filed: April 13, 2023
    Publication date: December 7, 2023
    Inventors: Yueh-Min CHEN, Ting-Yang WANG, Yu-Hsin LIN, Wen-Chieh WANG
  • Patent number: 11121720
    Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: September 14, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chan-Hsiang Weng, Hung-Yi Hsieh, Tzu-An Wei, Ting-Yang Wang
  • Patent number: 10944418
    Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: March 9, 2021
    Assignee: MediaTek Inc.
    Inventors: Ting-Yang Wang, Hung-Yi Hsieh, Tzu-An Wei, Tien-Yu Lo
  • Publication number: 20210044301
    Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.
    Type: Application
    Filed: July 20, 2020
    Publication date: February 11, 2021
    Inventors: Chan-Hsiang Weng, Hung-Yi Hsieh, Tzu-An Wei, Ting-Yang Wang
  • Publication number: 20200306185
    Abstract: An antibacterial colloid, comprising: a plurality of metal nanoparticles. wherein the plurality of metal nanoparticles have an average particle diameter less than 10 nm; a plurality of metal ions, wherein the plurality of metal ions have a concentration greater than 20 ppm; and a medium, wherein the medium comprises a protein component containing at least a functional group for reduction, wherein the antibacterial colloid is free from nitrate ions.
    Type: Application
    Filed: August 21, 2019
    Publication date: October 1, 2020
    Applicant: Kaohsiung Medical University
    Inventors: Chi-Jen Shih, Chung-Lin Lee, Yuan-Ting Yang-Wang, Yu-Ching Chiang, Yu-Hsuan Chen
  • Publication number: 20190238151
    Abstract: The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.
    Type: Application
    Filed: November 12, 2018
    Publication date: August 1, 2019
    Inventors: Ting-Yang Wang, Hung-Yi Hsieh, Tzu-An Wei, Tien-Yu Lo