Patents by Inventor Ting Yew
Ting Yew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230188552Abstract: This document describes a system and method for detecting the presence of Internet of Things (IoTs) from network traffic that has undergone a Network Address Translation (NAT) process, i.e., NATed network traffic, regardless of whether the network traffic comprises IP Flow Information Export (IPFIX) type of traffic or Domain Name System (DNS) type of traffic. Such a capability is crucial as the adoption rate of IoTs have increased exponentially over the past few years. In order to protect IoTs from cyber-attacks, one would first have to understand what type of IoTs are being used, and how many/how widely used these IoTs are. Once the IoT landscape has been defined, cyber defenders may then dedicate resources to identify and subsequently address vulnerabilities that may be in these IoTs.Type: ApplicationFiled: January 18, 2023Publication date: June 15, 2023Applicant: Ensign InfoSecurity Pte. Ltd.Inventors: Lee Joon SERN, Divakar SIVASHANKAR, Koh Ting YEW
-
Patent number: 10630269Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: GrantFiled: November 19, 2018Date of Patent: April 21, 2020Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 10382021Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: GrantFiled: July 24, 2017Date of Patent: August 13, 2019Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Publication number: 20190158073Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: ApplicationFiled: November 19, 2018Publication date: May 23, 2019Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 10141917Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: GrantFiled: July 24, 2017Date of Patent: November 27, 2018Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 10079054Abstract: Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.Type: GrantFiled: June 5, 2017Date of Patent: September 18, 2018Assignee: Lattice Semiconductor CorporationInventors: Senani Gunaratna, Brad Sharpe-Geisler, Ting Yew, Ronald L. Cline
-
Publication number: 20170324400Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Publication number: 20170324401Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 9735761Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: GrantFiled: January 30, 2015Date of Patent: August 15, 2017Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 9716491Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: GrantFiled: January 30, 2015Date of Patent: July 25, 2017Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 9543950Abstract: A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.Type: GrantFiled: January 30, 2015Date of Patent: January 10, 2017Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 9252755Abstract: A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.Type: GrantFiled: January 30, 2015Date of Patent: February 2, 2016Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Brad Sharpe-Geisler, Ting Yew, Senani Gunaratna
-
Publication number: 20160028383Abstract: A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.Type: ApplicationFiled: January 30, 2015Publication date: January 28, 2016Inventors: Brad Sharpe-Geisler, Ting Yew, Senani Gunaratna
-
Publication number: 20160028400Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: ApplicationFiled: January 30, 2015Publication date: January 28, 2016Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Publication number: 20160028401Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: ApplicationFiled: January 30, 2015Publication date: January 28, 2016Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Publication number: 20160020767Abstract: A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.Type: ApplicationFiled: January 30, 2015Publication date: January 21, 2016Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
-
Patent number: 8370691Abstract: In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.Type: GrantFiled: November 18, 2011Date of Patent: February 5, 2013Assignee: Lattice Semiconductor CorporationInventors: Chan-Chi Jason Cheng, Qin Wei, Ting Yew
-
Patent number: 8065574Abstract: A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.Type: GrantFiled: June 8, 2007Date of Patent: November 22, 2011Assignee: Lattice Semiconductor CorporationInventors: Chan-Chi Jason Cheng, Qin Wei, Ting Yew
-
Patent number: 7576563Abstract: Systems and methods are disclosed herein to provide high fan-out signal routing. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a secondary routing network adapted to route signals among the logic blocks. The secondary routing network may include a plurality of horizontal splines adapted to route signals within the programmable logic device; a plurality of vertical spline taps adapted to route signals within the programmable logic device; a plurality of common interface blocks adapted to route signals between the horizontal splines and the vertical spline taps; and a plurality of horizontal secondary branches adapted to route signals from the vertical spline taps to the logic blocks.Type: GrantFiled: February 6, 2007Date of Patent: August 18, 2009Assignee: Lattice Semiconductor CorporationInventors: Qin Wei, Chan-Chi Jason Cheng, Brad Sharpe-Geisler, Ting Yew
-
Patent number: 7401280Abstract: In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.Type: GrantFiled: May 18, 2007Date of Patent: July 15, 2008Assignee: Lattice Semiconductor CorporationInventors: Satwant Singh, Chi Nguyen, Ann Wu, Ting Yew