Abstract: Disclosed is an optical system using image restoration, including a light source, a pinhole, a testing platform, an image sensor and an image processing device. The pinhole is disposed on a light transmission path of the light source. The testing platform is disposed on the light transmission path of the light source and the pinhole is located between the light source and the testing platform. The testing platform is used to place a testing sample. The image sensor is disposed below the testing platform, and used to sense the testing sample so as to output an optical diffraction signal. The image processing device is electrically connected to the image sensor and used to perform signal processing and optical signal recognition on the optical diffraction signal of the testing sample so as to obtain a clear image of the testing sample.

Abstract: An integrated chip having an integrated function capable of providing cell image and biochemical detection is provided and includes a sequentially stacked and sealed laminate set. The laminate set includes an upper laminate, a middle laminate and a lower laminate. The upper laminate has one or more holes for sample injection and sample or air discharging of. The middle laminate includes at least two hollow structures that define an imaging chamber and a biochemical detection area. The lower laminate includes at least one filtering element and at least one electrode sensing element disposed in the biochemical detection. The filtering element is for blocking suspended particles, and the electrode sensing element has electrode terminals for connecting to instruments or equipment to perform the measurements and analysis of electrochemistry and impedance.

Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed herein including creating a photoresist mixture that includes a surfactant, and a base solvent; one or more boiling point modifying solvents having a boiling point higher in temperature than the base solvent; and one or more hydrophilicity modifying solvents that are more hydrophilic than the base solvent; depositing the photoresist mixture onto a substrate comprising a plurality of UBMLs using a wet film process; and performing a pre-bake process to cure the photoresist mixture.

Abstract: A high throughput lensless imaging method and system thereof are provided. The system mainly includes a light source, an optical panel, and an optical image sensing module. The optical panel corresponds to the light source and includes an optical pinhole that corresponds to the light source such that the light generated by the light source passes through the optical pinhole. The sensing unit is electrically connected to a computing unit that is used to compute after receiving the optical diffraction signal transmitted by the sensing unit, so as to perform the computation and reconstruction of an image.

Abstract: An electronic device having a function of automatically switching operation modes includes a circuit board, a first case, a second case, and a connector. The second case is assembled with the first case to form an accommodating space. The circuit board is disposed inside the accommodating space. The connector is disposed on the first case and applied for the circuit board. The connector can include a first contacting portion and a second contacting portion. The second contacting portion is equipped with the first contacting portion. The first contacting portion is pressed by the second case and drive deformation of the second contacting portion, and the second contacting portion contacts the circuit board to keep in a first operation mode. When the second case is removed from the first case, the second contacting portion is resiliently recovered and the circuit board is switched to a second operation mode.

Abstract: A semiconductor device assembly includes a die stack, a plurality of thermoset regions, and underfill material. The die stack includes at least first and second dies that each have a plurality of conductive interconnect elements on upper surfaces. A portion of the interconnect elements are connected to through-silicon vias that extend between the upper surfaces and lower surfaces of the associated dies. The plurality of thermoset regions each comprise a thin layer of thermoset material extending from the lower surface of the second die to the upper surface of the first die, and are laterally-spaced and discrete from each other. Each of the thermoset regions extends to fill an area between a plurality of adjacent interconnect elements of the first die. The underfill material fills remaining open areas between the interconnect elements of the first die.

Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed herein including creating a photoresist mixture that includes a surfactant, and a base solvent; one or more boiling point modifying solvents having a boiling point higher in temperature than the base solvent; and one or more hydrophilicity modifying solvents that are more hydrophilic than the base solvent; depositing the photoresist mixture onto a substrate comprising a plurality of UBMLs using a wet film process; performing a pre-bake process to cure the photoresist; and patterning the photoresist.

Abstract: Disclosed is an optical system using image restoration, including a light source, a pinhole, a testing platform, an image sensor and an image processing device. The pinhole is disposed on a light transmission path of the light source. The testing platform is disposed on the light transmission path of the light source and the pinhole is located between the light source and the testing platform. The testing platform is used to place a testing sample. The image sensor is disposed below the testing platform, and used to sense the testing sample so as to output an optical diffraction signal. The image processing device is electrically connected to the image sensor and used to perform signal processing and optical signal recognition on the optical diffraction signal of the testing sample so as to obtain a clear image of the testing sample.

Abstract: An integrated chip having an integrated function capable of providing cell image and biochemical detection is provided and includes a sequentially stacked and sealed laminate set. The laminate set includes an upper laminate, a middle laminate and a lower laminate. The upper laminate composed of one or more plates and having one or more holes for sample injection and sample or air discharging of. The middle laminate composed of one or more plates includes at least two hollow structures that define an imaging chamber and a biochemical detection area. The lower laminate includes at least one filtering element and at least one electrode sensing element disposed in the biochemical detection. The filtering element is for blocking suspended particles, and the electrode sensing element has electrode terminals for connecting to instruments or equipment to perform the measurements and analysis of electrochemistry and impedance.

Abstract: A high throughput lensless imaging method and system thereof are provided. The system mainly includes a light source, an optical panel, and an optical image sensing module. The light source is used to generate light with a specific wavelength to illuminate. The optical panel corresponds to the light source and includes an optical pinhole that corresponds to the light source such that the light generated by the light source passes through the optical pinhole. The position of the optical image sensing module corresponds to the other surface of the optical panel, and the optical image sensing module includes a sensing unit to receive an optical diffraction signal formed after the light source illuminates an object. The sensing unit is electrically connected to a computing unit that is used to compute after receiving the optical diffraction signal transmitted by the sensing unit, so as to perform the computation and reconstruction of an image.

Abstract: A directional antenna including a ground plane, a feeding element and a radiating element is provided. The feeding element is adjacent to the ground plane and includes a feeding point. A coupling gap is formed between the radiating element and the feeding element, and the radiating element includes a coupling point. Both the coupling point of the radiating element and the feeding point of the feeding element are at the perpendicular line of a ground plane. Further, a distance between the coupling point and an open end of the radiating element is smaller than 0.16? of a resonant frequency of the directional antenna.

Abstract: A tunable antenna includes a ground plane, a first radiation unit and a second radiation unit. The first radiation unit includes a feeding portion and a coupling portion. The feeding portion is electrically connected to a signal source. The second radiation unit surrounds a part of the coupling portion and includes a grounding end and a switch unit. The grounding end is electrically connected to the ground plane. The switch unit is electrically connected to the grounding end and the ground plane selectively.

Abstract: A directional antenna including a ground plane, a feeding element and a radiating element is provided. The feeding element is adjacent to the ground plane and includes a feeding point. A coupling gap is formed between the radiating element and the feeding element, and the radiating element includes a coupling point. Both the coupling point of the radiating element and the feeding point of the feeding element are at the perpendicular line of a ground plane. Further, a distance between the coupling point and an open end of the radiating element is smaller than 0.16? of a resonant frequency of the directional antenna.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract: Diffusion barrier layer is required during copper metallization in IC processing to prevent Cu from diffusion into the contacting silicon material and reacting to form copper silicide, which consumes Cu and deteriorates electrical conduction. With decreasing feature sizes of IC devices, such as those smaller than 90 nano-meter (nm), the thickness of diffusion barrier layer must be thinner than 10 nm. For example, a thickness of 2 nm will be called for at the feature size 27 nm. Disclosed in the present invention is ultra-thin barrier materials and structures based on tantalum silicon carbide, and its composite with another metallic layer Ru film. The retarding temperature, by which no evidence of copper diffusion can be identified, is 600˜850° C. depending on thickness, composition and film structure, at a thickness 1.6˜5 nm.