Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A backlight module includes a back board, a lamp board, a wavelength conversion film, an optical film, a coating layer and a reflective component. The back board includes a side wall. The lamp board is arranged on the back board, and includes plural light emitting units. The wavelength conversion film is arranged on the light emitting units. The optical film is arranged on the wavelength conversion film. The coating layer is arranged on the optical film, and adjacent to the optical film. The reflective component is arranged between the side wall and the optical film, and surrounds the wavelength conversion film and the optical film. At an optical wavelength of 450 nanometers, a brightness of a first surface of the reflective component is between 70 and 100, a first chromaticity thereof is between ?10 and 10, and a second chromaticity thereof is between ?10 and 10.

Abstract: An electronic apparatus includes at least one heat generating component and an immersion cooling system. The immersion cooling system includes a main tank and a liquid amount adjusting module. The main tank is adapted to contain a heat dissipation medium, and the heat generating component is disposed in the main tank to be immersed in the heat dissipation medium. The liquid adjusting module includes an auxiliary tank and a pump. The auxiliary tank is adjacent to the main tank, and the heat dissipation medium in the main tank is adapted to be overflowed into the auxiliary tank. The pump is disposed in the auxiliary tank and adapted to drive the heat dissipation medium in the auxiliary tank to flow into the main tank.

Abstract: The present invention provides an optical interposer for chip connection including a first total internal reflective layer, a waveguide and a second total internal reflective layer. The optical interposer is disposed above a first photonic integrated circuit chip and a second photonic integrated circuit chip, coupling the first photonic integrated circuit chip and the second photonic integrated circuit chip. The refractive indices of the first total internal reflective layer and the second total internal reflective layer are lower than the waveguide, making a light signal perform repetitive total internal reflections at the junctions between materials and advance in a zigzag shape within the waveguide, and further transmits between the first photonic integrated circuit chip and the second photonic integrated circuit chip.

Abstract: A pluggable optical packaging structure is provided, including: a substrate, a carrier ring, at least one optical connection assembly and a cover plate; the substrate includes at least one electronic integrated circuit (EIC) and at least one photonic integrated circuit (PIC); the carrier ring is located on the substrate, and the EIC and PIC are enclosed by the carrier ring; the optical connection assembly includes at least one socket, at least one connector, a plurality of optical fibers and at least one optical fiber array connector, the socket is located in a partial section of the carrier ring, the connector is in the socket, the optical fibers has one end coupled to the connector, the other end coupled to the fiber array connector, and is coupled to the PIC through the fiber array connector; the cover plate is located on the carrier ring and extends inwardly to above the PIC.

Abstract: A semiconductor device includes a semiconductor layered structure, an electrode unit, and an anti-adsorption layer. The electrode unit is disposed on an electrode connecting region of the semiconductor layered structure, and is a multi-layered structure. The anti-adsorption layer is disposed on a top surface of the electrode unit opposite to the semiconductor layered structure. Also disclosed herein is a light-emitting system including the semiconductor device.

Abstract: A light-coupling device includes an interposer, an optical chip, an optical waveguide element and a fiber array connector. The optical chip includes a waveguide layer with a light-emitting surface located aside the optical chip. The optical waveguide element includes an incident surface facing the light-emitting surface, an emergent surface located atop, and a reflective surface located inside. A light beam emitted horizontally from the light-emitting surface enters the optical waveguide element through the incident surface, totally reflected through the reflective surface and is output as a parallel light beam in the vertical direction through the emergent surface. The fiber array connector includes an optical waveguide lens and a plurality of fibers. The optical waveguide lens faces the emergent surface. One of both horizontal sides of the optical waveguide lens is a tilted reflective surface while the other is a light-coupling surface aligned with the fibers.

Abstract: An electronic apparatus includes at least one heat generating component and an immersion cooling system. The immersion cooling system includes a main tank and a liquid amount adjusting module. The main tank is adapted to contain a heat dissipation medium, and the heat generating component is disposed in the main tank to be immersed in the heat dissipation medium. The liquid adjusting module includes an auxiliary tank and a pump. The auxiliary tank is adjacent to the main tank, and the heat dissipation medium in the main tank is adapted to be overflowed into the auxiliary tank. The pump is disposed in the auxiliary tank and adapted to drive the heat dissipation medium in the auxiliary tank to flow into the main tank.

Abstract: The present invention provides an encryption determining method. The method includes the following steps: receiving a side channel signal; generating a filtered side channel signal by filtering noise within the side channel signal; generating a phasor signal by utilizing a filter to covert the filtered side channel signal; locating the encrypted segment by calculating a periodicity of the phasor signal utilizing a standard deviation window; extracting at least one encrypted characteristic from the encrypted segment; and generating an encryption analytic result by recognizing the at least one encrypted characteristic according to a characteristic recognition model; wherein the encryption analytic result includes a position of the encrypted segment within the side channel signal, and an encryption type corresponding to the side channel signal. The present invention is able to automatically and efficiently locate the encryption segment and analyze the encryption type corresponding to the side channel signal.

Abstract: The present invention provides a semiconductor structure including a substrate, a metal reflective layer, a UV glue layer, and an element. The metal reflective layer is placed on the surface of the substrate, and the UV glue layer is placed on the surface of the metal reflective layer. The element is manufactured by light-transparent material. The UV glue layer adheres the element to the metal reflective layer. By so, in the light-curing process, the curing of the UV glue is accelerated due to the metal reflective layer reflecting an ultraviolet ray.

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: A method for image-guided agriculture includes receiving images; processing the images to generate reflectance maps respectively corresponding to spectral bands; synthesizing the reflectance maps to generate a multispectral image including vegetation index information of a target area; receiving crop information in regions of the target area; and assessing crop conditions for the regions based on the identified crop information and the vegetation index information.

Abstract: A computer-implemented method is provided for cooling hard disk drives (HDDs). The method may include determining a threshold fan speed for one or more fans that provide cooling for HDDs based upon a target HDD vibration performance. The method may also include controlling the one or more fans, by a controller, to alternately run at a first fan speed for a first period and at the threshold fan speed for a second period, when the one or more fans reach the threshold fan speed. The first fan speed is higher than the threshold fan speed.

Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: An electronic apparatus includes at least one heat generating component and an immersion cooling system. The immersion cooling system includes a main tank and a liquid amount adjusting module. The main tank is adapted to contain a heat dissipation medium, and the heat generating component is disposed in the main tank to be immersed in the heat dissipation medium. The liquid adjusting module includes an auxiliary tank and a pump. The auxiliary tank is adjacent to the main tank, and the heat dissipation medium in the main tank is adapted to be overflowed into the auxiliary tank. The pump is disposed in the auxiliary tank and adapted to drive the heat dissipation medium in the auxiliary tank to flow into the main tank.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.