Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: An implantation device for prompt subcutaneous implantation of a sensor to measure a physiological signal of an analyte in a biofluid of a living body is disclosed. The implantation includes a housing, an implantation module, a detachable module and a bottom cover. The housing has a bottom opening, the implantation module including an implanting device and a needle extracting device, the detachable module includes the sensor configured to be detachably engaged with the implantation module and a base configured to mount the sensor thereon, wherein the base is separated from the sensor before sensor implantation; and the bottom cover configured to be detachably coupled to the bottom opening so that the housing and the bottom cover together form an accommodating space. The base includes an adhesive pad, and a release layer is attached to the adhesive pad.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a cached mapping table area and has a root mapping table. The processor determines whether a first node mapping table of the node mapping tables is temporarily stored in the cached mapping table area according to the root mapping table. In response to the first node mapping table is temporarily stored in the cached mapping table area, the processor accesses data according to the first node mapping table in the cached mapping table area, marks the modified first node mapping table through an asynchronous index identifier, and writes back the modified first node mapping table from the cached mapping table area to the memory array.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.

Abstract: An input device includes a digital pad and a digital pen. When a color picking switch of the digital pen is pressed by the user, the color picking switch generates a color picking signal. The color picking signal is transmitted to the digital pad or a computer through a wireless transmission module of the digital pen. According to the color picking signal, a color pointed through the digital pen is picked.

Abstract: An input device includes a digital pad and a digital pen. When a color picking switch of the digital pen is pressed by the user, the color picking switch generates a color picking signal. The color picking signal is transmitted to the digital pad or a computer through a wireless transmission module of the digital pen. According to the color picking signal, a color pointed through the digital pen is picked.

Abstract: A bed apparatus capable of automatically adjusting a bed surface based on a sleeping position is disclosed. The bed apparatus includes a multi-layer bed body including an upper layer and a lower layer, material of the upper layer being softer than the material of lower layer; a shoulder airbag fixedly embedded in the upper layer and supported by the lower layer; a waist airbag movably disposed on the upper layer; a sleeping position sensing unit generating a sensing signal in response to the sleeping position of a user; a control box receiving the sensing signal, and determining the sleeping position of the user based on the sensing signal, and controlling the shoulder airbag or the waist airbag to inflate or deflate, responsively.

Abstract: A mouse device includes a main body, an air cushion and a first hidden key. The first hidden key is located at a first side of the main body. The air cushion is located under the main body, and contactable with a working surface. The first hidden key is arranged between the main body and the air cushion. The first hidden key is not exposed outside. When the main body is leaned in a first direction and pressed down, the first hidden key is triggered to generate a first leaning signal. The first hidden key can be used to replace the key of the conventional keyboard. Due to the structure of the mouse device, the mouse device can be operated more intuitively.

Abstract: An AI-assisted operating system for an electronic sports game includes an input unit, a processing unit and an output unit. A current operating environment or a game scenario of playing the electronic sports game is sensed by the input unit from a perspective of an operator. The processing unit receives an information about the operating environment or the game scenario that is sensed by the input unit. After the operating environment or the game scenario is integrated and analyzed by the processing unit according to characteristics and requirements of the electronic sports game, a control command is generated. The output unit is installed in the equipment or environment for executing the electronic sports game. After the control command from the processing unit is received, the output unit prompts the operator or provides an operating message about the electronic sports game to the operator.