Abstract: Apparatuses, systems, and techniques are presented to generate digital content. In at least one embodiment, one or more neural networks are used to generate video information based at least in part upon voice information and a combination of image features and facial landmarks corresponding to one or more images of a person.

Abstract: Embodiments maintain a data pool that includes heterogeneous data sets, and receiving a first data batch of a data set from a data source into the data pool. Embodiments determine a current state of the data set based on a data set state diagram including a plurality of data set states, and identify a condition of the first data batch. Embodiments further set a data batch state for the first data batch, based on a data batch state diagram, and update the data batch state of a prior data batch received before the first data batch, based on the condition of the first data batch. Embodiments additionally transition the data set state diagram, based on the condition of the first data batch, to an updated data set state. Embodiments maintain a data state repository storing the data set state for each of the plurality of heterogeneous data sets.

Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.

Abstract: Apparatuses, systems, and techniques to generate a video using two or more images comprising objects to be included in the video. In at least one embodiment, objects are identified in two or more images using one or more neural networks, to generate a video to include the objects in the video.

Abstract: Apparatuses, systems, and techniques are presented to synthesize consistent images or video. In at least one embodiment, one or more neural networks are used to generate one or more second images based, at least in part, on one or more point cloud representations of one or more first images.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a cached mapping table area and has a root mapping table. The processor determines whether a first node mapping table of the node mapping tables is temporarily stored in the cached mapping table area according to the root mapping table. In response to the first node mapping table is temporarily stored in the cached mapping table area, the processor accesses data according to the first node mapping table in the cached mapping table area, marks the modified first node mapping table through an asynchronous index identifier, and writes back the modified first node mapping table from the cached mapping table area to the memory array.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.

Abstract: An input device includes a digital pad and a digital pen. When a color picking switch of the digital pen is pressed by the user, the color picking switch generates a color picking signal. The color picking signal is transmitted to the digital pad or a computer through a wireless transmission module of the digital pen. According to the color picking signal, a color pointed through the digital pen is picked.