Patents by Inventor Ting-Yu Shen
Ting-Yu Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118477Abstract: A backlight module includes a back board, a lamp board, a wavelength conversion film, an optical film, a coating layer and a reflective component. The back board includes a side wall. The lamp board is arranged on the back board, and includes plural light emitting units. The wavelength conversion film is arranged on the light emitting units. The optical film is arranged on the wavelength conversion film. The coating layer is arranged on the optical film, and adjacent to the optical film. The reflective component is arranged between the side wall and the optical film, and surrounds the wavelength conversion film and the optical film. At an optical wavelength of 450 nanometers, a brightness of a first surface of the reflective component is between 70 and 100, a first chromaticity thereof is between ?10 and 10, and a second chromaticity thereof is between ?10 and 10.Type: ApplicationFiled: September 11, 2023Publication date: April 11, 2024Inventors: Ling-Chieh SHEN, Ting-Ying WU, Yang-Ruei LI, Wen-Yu LIN
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Patent number: 11500018Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: GrantFiled: June 25, 2021Date of Patent: November 15, 2022Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ting-Yu Shen, Chien-Mo Li
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Publication number: 20210325458Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Ting-Yu Shen, Chien-Mo Li
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Patent number: 11073552Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: GrantFiled: September 30, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Patent number: 11047911Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: GrantFiled: August 14, 2019Date of Patent: June 29, 2021Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ting-Yu Shen, Chien-Mo Li
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Publication number: 20200132759Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.Type: ApplicationFiled: August 14, 2019Publication date: April 30, 2020Inventors: Ting-Yu Shen, Chien-Mo Li
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Publication number: 20200025826Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Patent number: 10429440Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: GrantFiled: July 26, 2017Date of Patent: October 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Publication number: 20190033366Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
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Patent number: 9385034Abstract: An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.Type: GrantFiled: April 11, 2007Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Ting-Yu Shen, Yung-Cheng Lu
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Patent number: 9087877Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.Type: GrantFiled: October 24, 2006Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chi Ko, Ting-Yu Shen, Keng-Chu Lin, Chia-Cheng Chou, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
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Patent number: 8324731Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.Type: GrantFiled: November 23, 2009Date of Patent: December 4, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
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Patent number: 8143162Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.Type: GrantFiled: July 10, 2009Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Yung-Cheng Lu, Hui-Lin Chang, Ting-Yu Shen, Hung Chun Tsai
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Publication number: 20100065969Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
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Patent number: 7646097Abstract: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.Type: GrantFiled: October 11, 2005Date of Patent: January 12, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
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Patent number: 7629273Abstract: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.Type: GrantFiled: September 19, 2006Date of Patent: December 8, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung Chun Tsai, Hui-Lin Chang, Ting-Yu Shen, Yung-Cheng Lu
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Publication number: 20090275195Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.Type: ApplicationFiled: July 10, 2009Publication date: November 5, 2009Inventors: Chen-Hua Yu, Yung-Cheng Lu, Hui-Lin Chang, Ting-Yu Shen, Hung Chun Tsai
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Publication number: 20080251928Abstract: An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Inventors: Hui-Lin Chang, Ting-Yu Shen, Yung-Cheng Lu
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Publication number: 20080096380Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.Type: ApplicationFiled: October 24, 2006Publication date: April 24, 2008Inventors: Chung-Chi Ko, Ting-Yu Shen, Keng-Chu Lin, Chia-Cheng Chou, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
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Publication number: 20080085607Abstract: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.Type: ApplicationFiled: September 19, 2006Publication date: April 10, 2008Inventors: Chen-Hua Yu, Hung Chun Tsai, Hui-Lin Chang, Ting-Yu Shen, Yung-Cheng Lu