Abstract: An adjustable marker reference device for identifying surgical instruments includes a base, an upper cover, a set of connecting rods, markers and a fixing button. The base has a first groove, and the upper cover has a second groove. The set of connecting rods is disposed between the base and the upper cover, and has two movable ends and a pivot point. The fixing button extends through the first groove, the pivot point and the second groove. When the fixing button is pressed, the set of connecting rods can freely bring the pivot point to slide along the first groove and the second groove. When the fixing button is not pressed, the pivot point is fixed at one of default positions. As the set of connecting rods is fixed, virtual lines between any two of the markers meet specific conditions.

Abstract: Provided are a method of individual tree crown segmentation from airborne LiDAR data using a novel Gaussian filter and energy function minimization. First, a dual Gaussian filter was designed with automated adaptive parameter assignment and a screening strategy for false treetops. This preserved the geometric characteristics of sub-canopy trees while eliminating false treetops. Second, anisotropic water expansion controlled by the energy function was applied to accurate crown segmentation. This utilized gradient information from the digital surface model and explored the morphological structures of tree crown boundaries as analogous to the maximal valley height difference from surrounding treetops. We demonstrate the generality of our approach using seven diverse plots in the subtropical Gaofeng Forest, China, coupled with ground verification.

Abstract: A predictive maintenance system and an implementation method thereof are provided. The system includes a mainboard, a sensing interface card coupled to the mainboard, and a predictive maintenance program. The mainboard includes a storage for storing a computer program and one or more processors for executing the computer program. The sensing interface card includes a sensor connection port that is configured to connect external device sensors with different connection interfaces and to receive detection values detected by the external device sensors, and a microprocessor for receiving the detection values to generate a failure prediction analysis result. The predictive maintenance program stored in the storage is executed by the processors.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: In an embodiment, a device includes: a first transistor including a first gate structure; a second transistor including a second gate structure, the second gate structure disposed above and coupled to the first gate structure; a third gate structure; a fourth gate structure, the fourth gate structure disposed above and coupled to the third gate structure; a gate isolation region between the first gate structure and the third gate structure, the gate isolation region disposed between the second gate structure and the fourth gate structure; and a cross-coupling contact extending beneath the gate isolation region, the first gate structure, and the third gate structure, the cross-coupling contact coupled to the first gate structure.

Abstract: A power converter includes an input circuit, a conversion circuit, an output circuit and a processor. The input circuit is configured to receive and detect a front stage power from a front stage device. The conversion circuit is coupled to the input circuit. The output circuit is coupled to the conversion circuit and configured to supply power to a back stage device. The processor is coupled to the input circuit, the conversion circuit and the output circuit. The processor is configured to determine whether the front stage power is stable, and is configured to handshake with the back stage device to confirm a conversion power agreed by the back stage device. The processor is further configured to control the conversion circuit to operate at the conversion power, so as to generate an output power to the back stage device.

Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.

Abstract: A method includes forming a lower transistor in a lower wafer, wherein the lower transistor includes a lower source/drain region, forming a contact plug electrically connecting to the lower source/drain region, and forming a metal line over the lower transistor. A first portion of the metal line is vertically aligned to the lower source/drain region. The method further includes bonding an upper wafer to the lower wafer, and forming an upper transistor in the upper wafer. The upper transistor includes an upper source/drain region, and is vertically aligned to a second portion of the metal line. A first interconnect structure is formed on the lower wafer and electrically connecting to the lower transistor. A second interconnect structure is formed on the upper wafer and electrically connecting to the upper transistor.

Abstract: A method includes forming a first transistor in a first wafer, wherein the first transistor includes a first source/drain region, forming a first bond pad electrically coupling to the first source/drain region, forming an second transistor in a second wafer, wherein the second transistor includes a second source/drain region, forming a second bond pad electrically coupling to the second source/drain region, and bonding the second wafer to the first wafer, with the second bond pad being bonded to the first bond pad.

Abstract: Provided are a video editing method, an electronic device and a medium. The video editing method includes: acquiring a first video; cutting the first video to obtain a plurality of segments; determining a plurality of labels respectively corresponding to the plurality of segments, each label among the plurality of labels selected from one of a first label, a second label, a third label or a fourth label, where the first label indicates singing, where the second label indicates speaking, where the third label indicates background music, and where the fourth label indicates a segment that does not correspond to the first label, the second label or the third label; determining a singing segment set based on the plurality of labels, the singing segment set including consecutive segments among the plurality of segments that correspond to the first label; and generating a second video based on the singing segment set.

Abstract: A replaceable membrane distillation module has a membrane distillation plate with an upper portion and a lower portion at two ends respectively. Two upper holes and two lower holes are defined through the upper portion and the lower portion at two ends respectively. A distillation portion is recessed in at least one side of the membrane distillation plate, and a distillation membrane covers on the distillation portion that a distillation space forms between the distillation portions and the distillation membrane. Multiple channels are disposed in the membrane distillation plate to communicate one of the upper holes, the distillation space and one of the lower flow holes. A blocking element is selectively combined with one of the upper holes or one of the lower flow holes.

Abstract: A machine posture inspection method and a machine posture inspection system are provided. The method includes: configuring an image capturing device to capture a current image of a region where a machine device is located, and configuring a processing device to: identify a reference marker in the current image and a first marker connected to the machine device; and calculate and obtain a current posture of the machine device according to the reference marker and the first marker; configure a motor encoder to measure an encoder signal associated with a motor; and determining whether or not the machine device is abnormal according to the current posture and the encoder signal.

Abstract: A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source/drain feature of the pass-gate transistor.

Abstract: A method of generating an image sample, which relates to a field of an artificial intelligence technology, in particular to fields of a deep learning technology and a computer vision technology. The method includes: generating a handwritten text image according to at least one handwritten sample image; and generating a target sample image with an annotation box according to the handwritten text image and a background image, where the annotation box is used to represent a region in which the handwritten text image is located in the background image. The present disclosure further provides a method of recognizing a text, an electronic device and a storage medium.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.

Abstract: A method for forming complementary FinFET (CFET) in a stacked configuration includes forming a recess in a stacked fin, growing a first epitaxial structure in the recess, etching the first epitaxial structure to remove a portion of the first epitaxial structure, forming a first isolation structure over the first epitaxial structure, and forming a second epitaxial structure over the first isolation structure. In another method, a dummy gate electrode over the stacked fin is etched, a first gate electrode deposited over the stacked fin, a portion of the first gate electrode recessed, and a second gate electrode formed over the first gate electrode. A CFET device includes a second channel region stacked over a first channel region, associated pairs of epitaxial structures on opposing sides of each of the first and second channel regions, and associated gate electrodes for each of the first and second channel regions.

Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.