Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: In an embodiment, a device includes: a first transistor including a first gate structure; a second transistor including a second gate structure, the second gate structure disposed above and coupled to the first gate structure; a third gate structure; a fourth gate structure, the fourth gate structure disposed above and coupled to the third gate structure; a gate isolation region between the first gate structure and the third gate structure, the gate isolation region disposed between the second gate structure and the fourth gate structure; and a cross-coupling contact extending beneath the gate isolation region, the first gate structure, and the third gate structure, the cross-coupling contact coupled to the first gate structure.

Abstract: A method includes forming a lower transistor in a lower wafer, wherein the lower transistor includes a lower source/drain region, forming a contact plug electrically connecting to the lower source/drain region, and forming a metal line over the lower transistor. A first portion of the metal line is vertically aligned to the lower source/drain region. The method further includes bonding an upper wafer to the lower wafer, and forming an upper transistor in the upper wafer. The upper transistor includes an upper source/drain region, and is vertically aligned to a second portion of the metal line. A first interconnect structure is formed on the lower wafer and electrically connecting to the lower transistor. A second interconnect structure is formed on the upper wafer and electrically connecting to the upper transistor.

Abstract: A method includes forming a first transistor in a first wafer, wherein the first transistor includes a first source/drain region, forming a first bond pad electrically coupling to the first source/drain region, forming an second transistor in a second wafer, wherein the second transistor includes a second source/drain region, forming a second bond pad electrically coupling to the second source/drain region, and bonding the second wafer to the first wafer, with the second bond pad being bonded to the first bond pad.

Abstract: A replaceable membrane distillation module has a membrane distillation plate with an upper portion and a lower portion at two ends respectively. Two upper holes and two lower holes are defined through the upper portion and the lower portion at two ends respectively. A distillation portion is recessed in at least one side of the membrane distillation plate, and a distillation membrane covers on the distillation portion that a distillation space forms between the distillation portions and the distillation membrane. Multiple channels are disposed in the membrane distillation plate to communicate one of the upper holes, the distillation space and one of the lower flow holes. A blocking element is selectively combined with one of the upper holes or one of the lower flow holes.

Abstract: A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source/drain feature of the pass-gate transistor.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: A method for forming complementary FinFET (CFET) in a stacked configuration includes forming a recess in a stacked fin, growing a first epitaxial structure in the recess, etching the first epitaxial structure to remove a portion of the first epitaxial structure, forming a first isolation structure over the first epitaxial structure, and forming a second epitaxial structure over the first isolation structure. In another method, a dummy gate electrode over the stacked fin is etched, a first gate electrode deposited over the stacked fin, a portion of the first gate electrode recessed, and a second gate electrode formed over the first gate electrode. A CFET device includes a second channel region stacked over a first channel region, associated pairs of epitaxial structures on opposing sides of each of the first and second channel regions, and associated gate electrodes for each of the first and second channel regions.

Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

Abstract: A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

Abstract: A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.