Abstract: A display device, including a backlight module (1). The backlight module (1) includes an optical film layer (2), the optical film layer (2) includes at least two diffusers (21) stacked in sequence, and the haze of each diffuser (21) is 80%-99%. The backlight module (1) further includes an LED light source (3), and the optical band of the LED light source (3) is greater than 455 nm. The display device further includes a cover plate (5) and at least one anti-reflection layer (7), the cover plate (5) is provided with an atomization layer (51), and the anti-reflection layer (7) is located on the side of the cover plate (5) facing away from a display panel (4).

Abstract: A timing controller includes: a field programmable gate array configured to generate a reference clock signal, and obtain at least one group of clock signals according to the reference clock signal. Each group of clock signals includes at least two clock signals, and a waveform of each clock signal is same as a waveform of the reference clock signal, and active levels in different clock signals are provided with a delay of a preset duration. The reference clock signal includes a first clock sub-signal for first duration and a second clock sub-signal for a second duration. At least one output interface group is connected to the field programmable gate array. Each output interface group includes at least two output interfaces, and each of the at least two output interfaces is configured to output one clock signal of a group of clock signals corresponding to the output interface group.

Abstract: A timing controller includes: a field programmable gate array configured to generate a reference clock signal, and obtain at least one group of clock signals according to the reference clock signal. Each group of clock signals includes at least two clock signals, and a waveform of each clock signal is same as a waveform of the reference clock signal, and active levels in different clock signals are provided with a delay of a preset duration. The reference clock signal includes a first clock sub-signal for first duration and a second clock sub-signal for a second duration. At least one output interface group is connected to the field programmable gate array. Each output interface group includes at least two output interfaces, and each of the at least two output interfaces is configured to output one clock signal of a group of clock signals corresponding to the output interface group.