Abstract: This disclosure is directed to a memory system that compensates for slow charge loss (SCL) encountered during a power off period. The memory system computes, during a power-on sequence of the memory device, a first value associated with reading data from an individual portion of the memory device and obtains a second value associated with reading data from the individual portion, the second value having been computed during a power-off sequence of the memory device. The memory system compares the first value with the second value to estimate a measure of SCL encountered while the memory device was powered off and reads the data from a plurality of portions of the memory device based on respective threshold voltages that compensate for the estimated measure of SCL.

Abstract: This disclosure is directed to a memory system that compensates for slow charge loss (SCL) encountered during a power off period. The memory system computes, during a power-on sequence of the memory device, a first value associated with reading data from an individual portion of the memory device and obtains a second value associated with reading data from the individual portion, the second value having been computed during a power-off sequence of the memory device. The memory system compares the first value with the second value to estimate a measure of SCL encountered while the memory device was powered off and reads the data from a plurality of portions of the memory device based on respective threshold voltages that compensate for the estimated measure of SCL.

Abstract: This disclosure is directed to a memory system that compensates for slow charge loss (SCL) encountered during a power off period. The memory system computes, during a power-on sequence of the memory device, a first value associated with reading data from an individual portion of the memory device and obtains a second value associated with reading data from the individual portion, the second value having been computed during a power-off sequence of the memory device. The memory system compares the first value with the second value to estimate a measure of SCL encountered while the memory device was powered off and reads the data from a plurality of portions of the memory device based on respective threshold voltages that compensate for the estimated measure of SCL.

Abstract: Aspects of the present disclosure configure a memory sub-system controller to detect extrinsic bitline defects. The controller stores a set of data in a set of memory components and performs a set of memory operations for detecting an empty page in a portion of the set of memory components. The controller determines, based on performing the set of memory operations, that the portion of the set of memory components is associated with an extrinsic bitline defect. The controller, in response to determining that the portion of the set of memory components is associated with the extrinsic bitline defect, prevents write operations to the portion of the set of memory components.