Patents by Inventor Tingjun Xie

Tingjun Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210286558
    Abstract: A system includes a memory component; and a processing device, operatively coupled with the memory component. The processing device is to perform operations including receiving a read request with respect to data stored at a physical address of the memory component; determining whether an indicator of the physical address is stored in a write transaction catalog; in response to determining that the physical address is stored in the write transaction catalog, determining a time difference between when the read request was received and when the data was written; reading the data stored at the physical address using a first read voltage level in response to determining that the time difference is less than a threshold criterion; and reading the data stored at the physical address using a second read voltage level in response to determining that the time difference is equal to or greater than the threshold criterion.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventors: Zhengang Chen, Tingjun Xie
  • Publication number: 20210286559
    Abstract: A method described herein involves identifying a first time associated with a read operation that retrieves data of a write unit at a memory sub-system, identifying a second time associated with a write operation that stored the data of the write unit at the memory sub-system, and performing a refresh operation for the data of the write unit at the memory sub-system based on a difference between the first time associated with the read operation and the second time associated with the write operation.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventors: Tingjun Xie, Zhengang Chen
  • Patent number: 11107550
    Abstract: A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Zhengang Chen
  • Publication number: 20210250051
    Abstract: A method includes receiving a request for host data, receiving a codeword that is associated with the host data, performing a decoding operation for a first portion of the codeword to generate a segment of decoded data, determining whether the segment of the decoded data satisfies the request for the host data, and in response to determining that the segment of the decoded data satisfies the request for the host data, terminating the decoding operation for remaining portions of the codeword.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
  • Publication number: 20210233603
    Abstract: A processing device in a memory sub-system determines a write-to-read delay time for a segment of a memory device read during a first read operation using a first read voltage level. The processing device further determines that the write-to-read delay time is associated with a second read voltage level and performs a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Tingjun Xie, Zhengang Chen
  • Publication number: 20210225442
    Abstract: A method is disclosed that includes causing a first set of a plurality of voltage pulses to be applied to memory cells of a memory device, a voltage pulse of the first set of the voltage pulses placing the memory cells of the memory device at a voltage level associated with a defined voltage state. The method also includes determining a set of bit error rates associated with the memory cells of the memory device in view of a data mapping pattern for the memory cells of the memory device, wherein the data mapping pattern assigns a voltage level associated with a reset state to at least a portion of the memory cells of the memory device. The method further includes determining whether to apply one or more second sets of the voltage pulses to the memory cells of the memory device in view of a comparison between the set of bit error rates for the memory cells and a previously measured set of bit error rates for the memory cells.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Murong Lang, Tingjun Xie, Zhenming Zhou
  • Publication number: 20210216402
    Abstract: Data to be stored at a memory sub-system can be received from a host system. A portion of the host data that includes user data and another portion of the host data that includes system metadata can be determined. A mapping for a data structure can be received that identifies locations of the data structure that are fixed with respect to an encoding operation and locations of the data structure that are not fixed with respect to the encoding operation. The data structure can be generated for the user data and system metadata based on the mapping, and an encoding operation can be performed on the data structure to generate a codeword.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
  • Patent number: 11056166
    Abstract: A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Seungjune Jeon, Zhengang Chen, Zhenlei Shen, Charles See Yeung Kwong
  • Patent number: 11037637
    Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
  • Publication number: 20210173743
    Abstract: Systems and methods are disclosed that are of retrieving, by a processing device, a codeword stored at a memory sub-system, determining parity data of the codeword, generating additional parity bits based on one or more bits of the parity data of the codeword, and generating host data by decoding the codeword using the additional parity bits.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
  • Patent number: 11023172
    Abstract: A system includes a memory component; and a processing device, operatively coupled with the memory component. The processing device is to receive a request to perform a read operation on data stored at a physical address of the memory component and determine whether the data satisfies a threshold criterion pertaining to when the data was written to the physical address. In response to the data satisfying the threshold criterion, the processing device is to perform the read operation on the data stored at the physical address using a first read voltage level, and in response to the data not satisfying the threshold criterion, perform the read operation on the data stored at the physical address using a second read voltage level.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhengang Chen, Tingjun Xie
  • Patent number: 11023171
    Abstract: A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Zhengang Chen
  • Patent number: 11004534
    Abstract: A processing device in a memory sub-system receives a read request from a host system, the read request identifying data stored in a segment of a memory component, and performs a first read operation on the segment using a first read voltage level. The processing device determines whether the data read during the first read operation was successfully decoded. If so, the processing device determines a write-to-read (W2R) delay time for the segment and determines whether the W2R delay time within a first W2R delay range, wherein the first W2R delay range represents a first plurality of W2R delay times corresponding to the first read voltage level. Responsive to the W2R delay time for the segment not falling within the first W2R delay range, the processing device performs a read refresh operation on at least a portion of the segment using an applicable read voltage level.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: May 11, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Tingjun Xie, Zhengang Chen
  • Patent number: 10992323
    Abstract: A decoder can receive an indication that a portion of a codeword has been decoded during a decoding operation. The decoder can determine a group of candidate output values of the decoding operation for the portion of the codeword, and eliminate one or more candidate output values from the group of candidate output values based on a decoded check code for each of the group of candidate output values. In response to determining that all of the candidate output values have been eliminated from the group of candidate output values, the decoder can terminate the decoding operation.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
  • Publication number: 20210118489
    Abstract: A method for performing a refresh operation based on system characteristics is provided. A The method includes determining that a current operation condition of a memory component is in a first state and detecting a change in the operation condition from the first state to a second state. The method further includes determining a range of the operation condition to which the second state belongs. The method further includes determining a refresh period associated with the range of the operation condition, the refresh period corresponding to a period of time between a first time when a write operation is performed on a segment of the memory component and a second time when a refresh operation is to be performed on the segment. The method further includes performing the refresh operation on the memory component according to the refresh period.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Zhenming Zhou, Tingjun Xie
  • Patent number: 10971228
    Abstract: A request to apply a plurality of voltage pulses to memory cells of a memory device can be received. A number of the voltage pulses can be applied the memory cells of the memory device, where a voltage pulse of the number of the voltage pulses places the memory cells of the memory device at a voltage level associated with a defined voltage state. A set of bit error rates associated with the memory cells of the memory device at the voltage level can be determined. Responsive to determining that the set of bit error rates does not satisfy a threshold condition, an additional number of the voltage pulses to the memory cells of the memory device can be applied.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Murong Lang, Tingjun Xie, Zhenming Zhou
  • Patent number: 10963342
    Abstract: Data to be stored at a memory sub-system can be received from a host system. A portion of the host data that includes user data and another portion of the host data that includes system metadata can be determined. A mapping for a data structure can be received that identifies locations of the data structure that are fixed with respect to an encoding operation and locations of the data structure that are not fixed with respect to the encoding operation. The data structure can be generated for the user data and system metadata based on the mapping, and an encoding operation can be performed on the data structure to generate a codeword.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
  • Publication number: 20210090683
    Abstract: A processing device in a memory system determines a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times. The processing device further determines whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion, and responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusts a read voltage level associated with the first range.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Inventors: Tingjun Xie, Zhengang Chen
  • Patent number: 10942809
    Abstract: Data to be stored at a memory sub-system can be received. A usage characteristic of the memory sub-system can be determined. The received data can be encoded to generate a codeword with a number of parity bits. A portion of the number of parity bits of the generated codeword can be removed based on the usage characteristic of the memory sub-system. Furthermore, the codeword can be stored without the removed portion of the number of parity bits.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
  • Publication number: 20210065781
    Abstract: A method for performing a refresh operation based on system characteristics is provided. The method includes determining that a current operating condition of a memory component is in a first state. The method also includes detecting a change in the operating condition from the first state to a second state. The method further includes setting a refresh period associated with the memory component based on the change of the operating condition. The refresh period corresponds to a period of time between a first time when a write operation is performed on a segment of the memory component and a second time when a refresh operation is to be performed on the segment. Moreover, the method includes performing the refresh operation according to the refresh period.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Zhenming Zhou, Tingjun Xie