Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

Abstract: In some implementations, a memory device may detect a first read failure associated with a page type and a memory section of the memory device. The memory device may perform multiple read recovery operations in a first order defined by a first sequence of read recovery operations. The memory device may identify a read recovery operation that results in successful recovery from the first read failure. The memory device may reorder the first sequence of read recovery operations to generate a second sequence of read recovery operations that prioritizes the read recovery operation. The memory device may detect a second read failure associated with the page type and the memory section. The memory device may perform one or more read recovery operations to recover from the second read failure in a second order defined by the second sequence of read recovery operations.

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

Abstract: A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.

Abstract: A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units, the processing device is configured to maintain state information of the memory device in response to performing each write operation of a plurality of write operations on the memory device; identify, in view of the state information, a candidate memory unit of the plurality of memory units that has been written to by at least a threshold fraction of the plurality of write operations performed on the memory device; and responsive to determining that a number of write operations performed on the memory device satisfies a threshold refresh criterion and that one or more of the plurality of memory units that are proximate to the candidate memory unit satisfy a failed bit threshold criterion, refresh data stored at the one or more of the plurality of memory units that are proximate to the candidate memory unit.

Abstract: A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page.

Abstract: A current cycle count associated with a memory sub-system is determined. The current cycle count is compared to a set of cycle count threshold levels to determine a current lifecycle stage of the memory sub-system. A temperature associated with the memory sub-system is measured. The temperature is compared to a set of temperature levels to determine a current temperature level of the memory sub-system. A write-to-read delay time corresponding to the current lifecycle stage and the current temperature level is determined.

Abstract: A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.

Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.

Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

Abstract: A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units; responsive to performing each write operation on a respective first memory unit of the memory device, the processing device is configured to identify a candidate memory unit that has been written to by a at least a threshold fraction of the plurality of write operations performed on the memory device; determine whether a threshold refresh criterion is satisfied; and responsive to determining that the threshold refresh criterion is satisfied, refresh data stored at one or more of the memory units that are proximate to the candidate memory unit.

Abstract: It is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.

Abstract: Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.

Abstract: In some implementations, a memory device may detect a first read failure associated with a page type and a memory section of the memory device. The memory device may perform multiple read recovery operations in a first order defined by a first sequence of read recovery operations. The memory device may identify a read recovery operation that results in successful recovery from the first read failure. The memory device may reorder the first sequence of read recovery operations to generate a second sequence of read recovery operations that prioritizes the read recovery operation. The memory device may detect a second read failure associated with the page type and the memory section. The memory device may perform one or more read recovery operations to recover from the second read failure in a second order defined by the second sequence of read recovery operations.

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

Abstract: A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

Abstract: A predefined data pattern is written using a plurality of values of a memory access parameter. A corresponding value of a data state metric associated with each value of a plurality of values of the memory access operation parameter is measured. An optimal value of the memory access operation parameter is selected from the plurality of values of the memory access operation parameter.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

Abstract: A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.