Abstract: A semiconductor device includes a semiconductor layer, a stack structure over the semiconductor layer, a first contact structure, and a second contact structure. The stack structure includes alternating first layers and first dielectric layers. The stack structure includes a first portion and a second portion adjacent to the first portion, the first layers of the first portion include second dielectric layers, and the first layers of the second portion include conductive layers. The first contact structure extends through the first portion and the semiconductor layer. The second contact structure extends through a part of the first portion and connects with one of the conductive layers.

Abstract: In one embodiment, an integrated circuit device includes a substrate and a component coupled to the substrate. The substrate includes first reservoirs comprising Gallium-based liquid metal (LM), second reservoirs, first channels between the first reservoirs, and second channels between the second reservoirs and respective first reservoirs. The component includes circuitry and conductive contacts connected to the circuitry. Each contact defines a cavity and a portion of each conductive contact is within a respective first reservoir of the substrate such that it is in contact with the LM in the first reservoir. The component further includes dielectric lines between the conductive contacts, and each dielectric line is at least partially within a respective first channel of the substrate.

Abstract: The present invention relates to a bismuth tungstate/bismuth sulfide/molybdenum disulfide heterojunction ternary composite material and a preparation method and application thereof. The composite material is composed of bismuth tungstate, bismuth sulfide and molybdenum disulfide in an ordered layered way, Bi2WO6 is an orthorhombic system, Bi2S3 is a p-type semiconductor located on a (130) crystal face, MoS2 is a layered transition metal sulfide located on a (002) crystal face, the whole composite material is of a spherical structure with an unsmooth surface, and a layer of nanosheets uniformly grow on an outer layer. The average particle size of composite materials is in the range of 2.4-2.6 ?m. The spherical Bi2WO6/Bi2S3/MoS2 heterojunction ternary composite material prepared in the present invention has good adsorption of Cr(VI) and high catalytic reduction ability under visible light.

Abstract: Compliant inserts for pin dipping processes are disclosed herein. An example apparatus disclosed herein includes a pin array to transfer material to a package substrate of an integrated circuit package, a cover plate, an elastic insert to be disposed between the cover plate and the pin array.

Abstract: According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first wafer. The first wafer may include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. A pointing direction of the first mark may be the same as an extending direction of the first dicing lane. A cleavage plane of the first wafer may be parallel to the pointing direction of the first mark. The pointing direction of the first mark may be an extending direction of a line of symmetry of the first wafer. The semiconductor structure may include a second wafer. The second wafer and the first wafer may be disposed in a stack. The second wafer may be a plurality of memory array chips.

Abstract: A method for controlling a regenerated chip, a regenerated chip, and a regenerated ink cartridge are provided. The regenerated chip is electrically connected to a printer by means of a first data signal wire and a logic signal wire, and is electrically connected to an ink cartridge chip by means of a second data signal wire. The method for controlling a regenerated chip includes: detecting an operation command sent by the printer by means of the first data signal wire and the logic signal wire; and when it is detected that the operation command is not a selected operation command, sending a data signal to the ink cartridge chip by means of the second data signal wire, wherein the data signal instructs the ink cartridge chip to communicate with the printer.

Abstract: Embodiments disclosed herein include socket interconnects with liquid metal. In an embodiment, a board comprises a substrate. A pad may be provided over the substrate. In an embodiment, a confinement layer is over the substrate, where the confinement layer defines a cavity over the pad. In an embodiment, a liquid metal is on the pad within the cavity. In an embodiment, a protective layer is provided over the liquid metal.

Abstract: Methods, apparatus, systems, and articles of manufacture to place balls for second level interconnects of integrated circuit packages are disclosed. An example apparatus includes a ball head including a first surface having an array of holes. The array of holes hold a corresponding array of solder balls to be placed on a package substrate of an integrated circuit package. The apparatus also includes a protrusion extending away from the surface of the ball head. The protrusion is positioned relative to the holes to contact a second surface of the package substrate when the solder balls are to be placed on the package substrate.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes a plurality of semiconductor channels in the plurality of petals, respectively.

Abstract: Provided in the present application are a random access method, and an electronic device and a storage medium. In the method, for different services, different preamble ranges are delineated and different priorities are set, such that each user terminal selects a preamble from within a preamble range corresponding to a service that is borne by the user terminal itself and sends the preamble to a base station; and the base station responds to the access of the user terminals according to the priorities of services corresponding to the acquired preambles, and the access of the user terminal that bears a service having a high priority (having a higher requirement for a delay) is preferentially responded to thereby.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a charge trapping layer, a tunneling layer, a semiconductor channel, and a channel plug. The channel plug is above and in contact with the charge trapping layer, the tunneling layer, and the semiconductor channel.

Abstract: The present disclosure provides a method of processing a semiconductor device having a stack formed over a source sacrificial layer above a substrate, a channel structure extending vertically through the stack and the source sacrificial layer, a gate line cut trench extending vertically through the stack, and a spacer layer covering uncovered top and side surfaces of the stack. The method can include exposing a lower sidewall of the channel structure by removing the source sacrificial layer, forming a protection layer on all uncovered surfaces, exposing a channel layer of the channel structure by removing a first portion of the protection layer and an insulating layer of the channel structure, forming an initial source connection layer over the exposed channel layer, exposing the substrate by removing a second portion of the protection layer, and forming a source connection layer over the initial source connection layer and the exposed substrate.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of interleaved conductive layers and dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and having a plurality of protruding portions abutting the conductive layers and a plurality of normal portions abutting the dielectric layers. Each of the plurality of channel structures includes a blocking layer along a sidewall of the channel structure, and a storage layer over the blocking layer. The storage layer includes a plurality of charge trapping structures in the protruding portions of the channel structure, and a plurality of protecting structures in the normal portions of the channel structure and connecting the plurality of charge trapping structures.

Abstract: A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening that exposes the sacrificial layer, removing the sacrificial layer to create a cavity and expose a part of the channel hole structure, forming a semiconductor layer to fill the cavity, filling the opening with a filling structure, and forming a second dielectric stack over the filling structure. The opening is made for a gate line slit (GLS) structure.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers and comprising a conductive layer sandwiched between two dielectric layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer.

Abstract: The present disclosure provides a three-dimensional memory comprising: a storage channel structure vertically penetrating a plurality of stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising: a block layer in contact with the select gate structure, an insulating layer covering the block layer, and a second channel layer in contact with the insulating layer and the first channel layer.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, the three-dimensional memory device including: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer; wherein an outer sidewall of the second channel layer is in contact with an inner sidewall of the first channel layer.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure of alternating insulating layers and word line layers, a first top select gate (TSG) layer over the stack structure, and a separation structure extending through the first TSG layer, where the first TSG layer is divided by the separation structure into a first sub TSG layer and a second sub TSG layer. The semiconductor device includes a conductive layer positioned between the first sub TSG layer and the separation structure, and between the second sub TSG layer and the separation structure.

Abstract: A three-dimensional (3D) memory device includes a memory stack including conductive layers and dielectric layers interleaving the conductive layers, and a channel structure extending through the memory stack along a vertical direction. The channel structure has a plurality of protruding portions protruding along a lateral direction and facing the conductive layers, respectively, and a plurality of normal portions facing the dielectric layers, respectively, without protruding along the lateral direction. The channel structure includes a plurality of blocking structures in the protruding portions, respectively, and a plurality of storage structures in the protruding portions and over the plurality of blocking structures, respectively. A vertical dimension of each of the blocking structures is nominally the same as a vertical dimension of a respective one of the storage structures over the blocking structure.