Abstract: A shift register according to the present disclosure may specifically include multi-level shift register units, a first connecting TFT set and a second connecting TFT set. In the multi-level shift register units, control signal input ends of odd-number-level shift register units are inputted with a first control signal and control signal input ends of even-number-level shift register units are inputted with a second control signal. Connecting TFTs in the first connecting TFT set and the second connecting TFT set are configured to achieve an electrical connection between gate electrode signal output ends of odd-number-level shift register units and even-number-level shift register units in the shift register under a control of a control signal transmitted by a timing controller.