Patents by Inventor Tingting XIA

Tingting XIA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11998714
    Abstract: A tattoo needle includes: a needle piercing portion. The needle piercing portion includes at least one piercing projection, wherein each of the at least one piercing projection comprises at least one substrate and a plurality of needle teeth. The number of the at least one substrate is one, the plurality of needle teeth is arranged on a side surface of the one substrate, the plurality of needle teeth are arranged in a row on the substrate, a central axis of each of the plurality of needle teeth is perpendicular to the side surface of the one substrate; and the one substrate is configured to limit a piercing depth that the plurality of needle teeth pierces into a skin.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: June 4, 2024
    Inventor: Tingting Xia
  • Patent number: 11998713
    Abstract: An introduction needle includes a needle piercing portion. The needle piercing portion comprises a piercing projection, the piercing projection includes a substrate and a needle tooth, the needle tooth is fixedly arranged on a side surface of a side of the substrate, a central axis of the needle tooth is perpendicular to the side surface of the substrate.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: June 4, 2024
    Inventor: Tingting Xia
  • Publication number: 20240130120
    Abstract: The present disclosure provides a three-dimensional memory comprising: a storage channel structure vertically penetrating a plurality of stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising: a block layer in contact with the select gate structure, an insulating layer covering the block layer, and a second channel layer in contact with the insulating layer and the first channel layer.
    Type: Application
    Filed: December 28, 2022
    Publication date: April 18, 2024
    Inventors: Jiayi Liu, Tingting Gao, Xiaoxin Liu, Xiaolong Du, Changzhi Sun, Zhiliang Xia
  • Publication number: 20240130130
    Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers and comprising a conductive layer sandwiched between two dielectric layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer.
    Type: Application
    Filed: December 28, 2022
    Publication date: April 18, 2024
    Inventors: Jiayi Liu, Tingting Gao, Changzhi Sun, Xiaolong Du, Xiaoxin Liu, Zhiliang Xia
  • Publication number: 20240130129
    Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, the three-dimensional memory device including: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer; wherein an outer sidewall of the second channel layer is in contact with an inner sidewall of the first channel layer.
    Type: Application
    Filed: December 28, 2022
    Publication date: April 18, 2024
    Inventors: Jiayi Liu, Tingting Gao, Xiaoxin Liu, Xiaolong Du, Changzhi Sun, Zhiliang Xia
  • Publication number: 20240099008
    Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Tingting GAO, ZhiLiang XIA, Xiaoxin LIU, Xiaolong DU, Changzhi SUN, Jiayi LIU, ZongLiang HUO
  • Publication number: 20240081069
    Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure of alternating insulating layers and word line layers, a first top select gate (TSG) layer over the stack structure, and a separation structure extending through the first TSG layer, where the first TSG layer is divided by the separation structure into a first sub TSG layer and a second sub TSG layer. The semiconductor device includes a conductive layer positioned between the first sub TSG layer and the separation structure, and between the second sub TSG layer and the separation structure.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Tingting GAO, ZhiLiang XIA, ZongLiang HUO
  • Publication number: 20230414914
    Abstract: An introduction needle includes a needle piercing portion. The needle piercing portion comprises a piercing projection, the piercing projection includes a substrate and a needle tooth, the needle tooth is fixedly arranged on a side surface of a side of the substrate, a central axis of the needle tooth is perpendicular to the side surface of the substrate.
    Type: Application
    Filed: September 6, 2023
    Publication date: December 28, 2023
    Inventor: Tingting Xia
  • Publication number: 20230414915
    Abstract: A tattoo needle includes: a needle piercing portion. The needle piercing portion includes at least one piercing projection, wherein each of the at least one piercing projection comprises at least one substrate and a plurality of needle teeth. The number of the at least one substrate is one, the plurality of needle teeth is arranged on a side surface of the one substrate, the plurality of needle teeth are arranged in a row on the substrate, a central axis of each of the plurality of needle teeth is perpendicular to the side surface of the one substrate; and the one substrate is configured to limit a piercing depth that the plurality of needle teeth pierces into a skin.
    Type: Application
    Filed: September 6, 2023
    Publication date: December 28, 2023
    Inventor: Tingting Xia
  • Patent number: 11286506
    Abstract: A novel gene editing system developed based on the gene cas3 in the type I-B CRISPR-Cas system in the chromosome of Streptomyces virginiae IBL14 enables the gene editing of a type I CRISPR-Cas system on biological cell genomes for the first time. In the system, Cas3 can specifically cleave a DNA fragment of interest guided by crRNA or t-DNA. The new approach can be applied to rapid, simple and correct genome editing of prokaryotic and eukaryotic cells, which provides novel supplements and selections for the commercialized gene editing system developed based on Cas9 in type II.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 29, 2022
    Assignee: ANHUI UNIVERSITY
    Inventors: Wangyu Tong, Yanyan Tang, Tingting Xia
  • Publication number: 20190376089
    Abstract: A novel gene editing system developed based on the gene cas3 in the type I-B CRISPR-Cas system in the chromosome of Streptomyces virginiae IBL14 enables the gene editing of a type I CRISPR-Cas system on biological cell genomes for the first time. In the system, Cas3 can specifically cleave a DNA fragment of interest guided by crRNA or t-DNA. The new approach can be applied to rapid, simple and correct genome editing of prokaryotic and eukaryotic cells, which provides novel supplements and selections for the commercialized gene editing system developed based on Cas9 in type H.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 12, 2019
    Applicant: ANHUI UNIVERSITY
    Inventors: Wangyu TONG, Yanyan TANG, Tingting XIA
  • Patent number: 8972812
    Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 3, 2015
    Assignee: University of Electronic Science and Technology of China
    Inventors: Yajuan He, Tingting Xia, Tao Luo, Wubing Gan, Bo Zhang
  • Publication number: 20140304572
    Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.
    Type: Application
    Filed: June 27, 2013
    Publication date: October 9, 2014
    Inventors: Yajuan HE, Tingting XIA, Tao LUO, Wubing GAN, Bo ZHANG