Patents by Inventor Tino Karczewski

Tino Karczewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12113000
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: October 8, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ajay Poonjal Pai, Tino Karczewski, Adrian Lis
  • Publication number: 20230178460
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 8, 2023
    Inventors: Ajay Poonjal Pai, Tino Karczewski, Adrian Lis
  • Patent number: 11004764
    Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Tao Hong, Tino Karczewski, Matthias Lassmann, Christian Schweikert
  • Publication number: 20200273778
    Abstract: A power semiconductor arrangement includes first and second power semiconductor modules. Each power semiconductor module has a first main side and an opposing second main side. The power semiconductor modules are arranged such that a main side of the first power semiconductor module and a main side of the second power semiconductor module are facing each other. The power semiconductor arrangement further includes a cooler housing configured for direct liquid cooling of the power semiconductor modules. The cooler housing includes a fluid channel. At least one main side of the first power semiconductor module forms a sidewall of the fluid channel. A flow direction in the fluid channel along the first main side and a flow direction along the second main side of the first power semiconductor module are oriented in opposite directions.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 27, 2020
    Inventors: Juergen Hoegerl, Tino Karczewski, Michael Scheffer, Christian Schweikert
  • Publication number: 20200035579
    Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 30, 2020
    Inventors: Juergen Hoegerl, Tao Hong, Tino Karczewski, Matthias Lassmann, Christian Schweikert