Patents by Inventor Tiong C. Go

Tiong C. Go has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5104820
    Abstract: A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips.
    Type: Grant
    Filed: June 24, 1991
    Date of Patent: April 14, 1992
    Assignee: Irvine Sensors Corporation
    Inventors: Tiong C. Go, deceased, Joseph A. Minahan, Stuart N. Shanken
  • Patent number: 4983533
    Abstract: A high-density electronic module is disclosed, which is suitable for use as a DRAM, SRAM, ROM, logic unit, arithmetic unit, etc. It is formed by stacking integrated-circuit chips, each of which carries integrated circuitry. The chips are glued together, with their leads along one edge, so that all the leads of the stack are exposed on an access plane. Where heat extraction augmentation is needed, additional interleaved layers are included in the stacks which have high thermal conductivity, and are electrical insulators. These interleaved layers may carry rerouting electrical conductors. Bonding bumps are formed at appropriate points on the access plane. A stack-supporting substrate is provided with suitable circuitry and bonding bumps on its face. A layer of insulation is applied to either the access plane or stack-supporting substrate, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied.
    Type: Grant
    Filed: October 28, 1987
    Date of Patent: January 8, 1991
    Assignee: Irvine Sensors Corporation
    Inventor: Tiong C. Go
  • Patent number: 4912545
    Abstract: A bump bonding process and product are disclosed in which both pressure and heating are used in situations where the temperature should not exceed a predetermined amount, e.g., bonding of a photoconductor array to a module containing electronic processing devices. The bonding process involves eutectic alloying of indium and bismuth, allowing welding of the bumps at a temperature substantially below the two metals' melting points. In one version of the invention, bumps on adjacent substrates are directly aligned. In another version, each bump on one substrate is wedged between a pair of bumps on the other substrate.
    Type: Grant
    Filed: September 16, 1987
    Date of Patent: March 27, 1990
    Assignee: Irvine Sensors Corporation
    Inventor: Tiong C. Go
  • Patent number: 4764846
    Abstract: A high density electronic package is disclosed in which a stack of layer-like sub-modules have their edges secured to a stack-carrying substrate, the latter being in a plane perpendicular to the planes in which the sub-modules extend. Each sub-module has a cavity, inside which one or more IC chips are located. Each cavity-providing sub-module may be formed either by securing a rectangular frame to a chip-carrying substrate, or by etching a cavity in a single piece of material. In the latter case, the chips are mounted on the flat surface of one sub-module, and located inside the cavity of the next sub-module.
    Type: Grant
    Filed: January 5, 1987
    Date of Patent: August 16, 1988
    Assignee: Irvine Sensors Corporation
    Inventor: Tiong C. Go
  • Patent number: 4706166
    Abstract: A high-density electronic module is disclosed, which is suitable for use as a DRAM, SRAM, ROM, logic unit, arithmetic unit, etc. It is formed by stacking integrated-circuit chips, each of which carries integrated circuitry. The chips are glued together, with their leads along one edge, so that all the leads of the stack are exposed on an access plane. Bonding bumps are formed at appropriate points on the access plane. A supporting substrate, formed of a light transparent material, such as silicon, is provided with suitable circuitry and bonding bumps on its face. A layer of insulation is applied to either the access plane or the substrate face, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied. The substrated face is placed on the access plane of the stack, their bonding bumps are microscopically aligned, and then bonded together under heat and/or pressure.
    Type: Grant
    Filed: April 25, 1986
    Date of Patent: November 10, 1987
    Assignee: Irvine Sensors Corporation
    Inventor: Tiong C. Go