Abstract: An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

Abstract: Diodes, transistors, and other devices having a class IV channel region and a class III-V drift region are described. The class IV channel region, such as a Si channel region, is able to provide all associated advantages, such as ease of manufacturing of many different types of devices, using cost-effective materials and techniques. Meanwhile, the III-V drift region provides substantially lower Ron_sp than a conventional class IV drift region, and substantially enhances the operational behaviors of resulting devices, without sacrificing other parameters, such as size or breakdown voltage.

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

Abstract: According to an aspect, a semiconductor design system includes at least one neural network including a first predictive model and a second predictive model, where the first predictive model is configured to predict a first characteristic of a semiconductor device, and the second predictive model is configured to predict a second characteristic of the semiconductor device. The semiconductor design system includes an optimizer configured to use the neural network to generate a design model based on a set of input parameters, where the design model includes a set of design parameters for the semiconductor device such that the first characteristic and the second characteristic achieve respective threshold conditions.

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

Abstract: Implementations of a system configured for operation of a motor may include a motor controller coupled with a memory, the motor controller configured to be coupled with a motor. The motor controller may be configured to store a set of control parameters in the memory, the set of control parameters generated using a deep reinforcement learning agent and data associated with one or more parameters of the motor. The set of control parameters may be configured to define an optimized operating area for the motor.

Abstract: In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.

Abstract: In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.

Abstract: In one general aspect, an apparatus can include a junction-less, gate-controlled voltage clamp device having a gate terminal coupled to a voltage reference device.

Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

Abstract: In one general aspect, an apparatus can include a junction-less, gate-controlled voltage clamp device having a gate terminal coupled to a voltage reference device.

Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

Abstract: A multi-stage optically-triggered power system. At least one triggering stage is responsive to at least one optical trigger to directly create photogeneration of carriers in the at least one triggering stage and thus generate at least one output signal. At least one main power device stage coupled to the at least one triggering stage is responsive to the at least one generated output signal to activate the at least one main power device stage. The at least one triggering stage and the at least one main power device stage may be monolithically integrated.

Abstract: A power device is provided in an optically-triggered power system having a controller for generating electrical control signals and a converter for converting the electrical control signals to optical control signals. The power device includes a pair of terminals and a P-body region provided adjacent an N+ source region. An optical window is provided at least partially over the P-body region, and an N? drift region is provided between the two terminals. The P-body region causes current to conduct between the first and second terminal through the N? drift region when an optical control signal is incident on the optical window.

Abstract: A power device is provided in an optically-triggered power system having a controller for generating electrical control signals and a converter for converting the electrical control signals to optical control signals. The power device includes a pair of terminals and a P-body region provided adjacent an N+ source region. An optical window is provided at least partially over the P-body region, and an N? drift region is provided between the two terminals. The P-body region causes current to conduct between the first and second terminal through the N? drift region when an optical control signal is incident on the optical window.

Abstract: A multi-stage optically-triggered power system. At least one triggering stage is responsive to at least one optical trigger to directly create photogeneration of carriers in the at least one triggering stage and thus generate at least one output signal. At least one main power device stage coupled to the at least one triggering stage is responsive to the at least one generated output signal to activate the at least one main power device stage. The at least one triggering stage and the at least one main power device stage may be monolithically integrated.