Patents by Inventor Tito MANGAOANG, JR.

Tito MANGAOANG, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Protection from ESD during the manufacturing process of semiconductor chips
    Patent number: 10672689
    Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: June 2, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Frederick Ray Gomez, Tito Mangaoang, Jr., Jefferson Talledo
  • PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCTOR CHIPS
    Publication number: 20190326201
    Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Frederick Ray GOMEZ, Tito Mangaoang, JR., Jefferson Talledo
  • Protection from ESD during the manufacturing process of semiconductor chips
    Patent number: 10388594
    Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Frederick Ray Gomez, Tito Mangaoang, Jr., Jefferson Talledo
  • PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCTOR CHIPS
    Publication number: 20190006266
    Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Frederick Ray GOMEZ, Tito MANGAOANG, JR., Jefferson TALLEDO