Abstract: An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.

Abstract: An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited on a partially or completely removable carrier; and a dielectric layer encapsulating the internal conductive trace layer through a lamination process or a printing process. The top surface of the topmost internal conductive trace layer and bottom surface of the bottommost internal conductive trace layer are exposed and not covered by the dielectric layer. External conductive trace layer can also be deposited outside of the dielectric layer. The internal conductive trace layers are deposited through plating or printing of an electronically conductive material, whereas the external conductive trace layer is deposited through electroless and electroplating, or printing of the electronically conductive layer.

Abstract: An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

Abstract: An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

Abstract: An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited on a partially or completely removable carrier; and a dielectric layer encapsulating the internal conductive trace layer through a lamination process or a printing process. The top surface of the topmost internal conductive trace layer and bottom surface of the bottommost internal conductive trace layer are exposed and not covered by the dielectric layer. External conductive trace layer can also be deposited outside of the dielectric layer. The internal conductive trace layers are deposited through plating or printing of an electronically conductive material, whereas the external conductive trace layer is deposited through electroless and electroplating, or printing of the electronically conductive layer.