Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit.The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

Abstract: A process for fabricating CMOS integrated devices includes forming an n-type deep well diffusion region in a surface of a p-type monocrystalline silicon substrate. Transistor devices having a p-type channel region are formed within the deep well diffusion regions, and transistor devices having an n-type channel region are formed external the deep well diffusion regions. The improvement of the present invention includes the step of performing an unmasked ion implantation of boron over the entire surface of the monocrystalline silicon substrate after having formed the deep well diffusion regions in order to effect simultaneously a partial compensation of a superficial doping level of the deep well diffusion region and an enrichment of a superficial doping level of the monocrystalline silicon substrate external the deep well diffusion region.