Abstract: The invention provides a system and method that reduces the tediousness of the manual alignment process. Users select correspondences between projectors or components of a projector, to form a common coordinate. Using models of the display system, and projectors, the common coordinate system can be mapped quickly to the entire display. The process avoids a need to measure screen points, and allows the user to move significantly fewer points. Alternatively, the invention allows introduction of machine-vision style algorithms into manual calibration techniques to improve performance. This overcomes the tediousness of prior systems by introducing models of the display into the manual alignment process, allowing selection of a small number of points on each projector, and avoiding selection of precisely measured screen points. The system conversely finds correspondences between projectors, allowing mapping of the projectors into a common coordinate system, and quick warping of the coordinate system to the screen.

Abstract: Aspects of the methods and apparatus relate to transferring a received Voice-over-Long Term Evolution (VoLTE) call to a High Speed Packet Access (HSPA) packet-switched (PS) based voice call. One aspect of the methods and apparatus include receiving a VoLTE call from a network and identifying uplink VoLTE handover characteristics of the VoLTE call for an uplink transmission to the network and a downlink VoLTE handover characteristics for a downlink transmission from the network. The aspect includes configuring uplink HSPA PS based handover characteristics that emulate the uplink VoLTE handover characteristics for the uplink transmission and configuring downlink HSPA PS based handover characteristics that emulate the downlink VoLTE handover characteristics for the downlink transmission.

Abstract: A pico projection fixing module includes a bracket main body, at least two collimator lenses, and at least two color light sources. The bracket main body includes an upper part, a lower part, a connecting part and at least two assembling seats. The upper part and the lower part are located at bilateral sides of the connecting part. Each of the assembling seats includes an opening and a clamping part. The opening is formed on the connecting part. The clamping part is disposed on the upper part and the lower part. The at least two collimator lenses are installed on the connecting part and corresponded to the corresponding openings. The at least two color light sources are installed on the corresponding clamping parts and aligned with the corresponding collimator lenses. The clamping parts corresponding to the assembling seats are separated from each other.

Abstract: A memory includes a plurality of memory cells. A first line is over the plurality of memory cells. The first line in a first layout section includes a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A second line is over the plurality of memory cells. The second line in the first layout section includes the first metal layer and a third metal layer. The third metal layer is over the second metal layer The first line is electrically isolated from the second line. The first line and the second line extend in a same direction.

Abstract: An active organic electroluminescence device back panel and a manufacturing method thereof are disclosed. The device back panel includes: a substrate, a plurality of active TFT pixel arrays formed on the substrate, and organic planarization layers, organic electroluminescence electrodes, pixel definition layers, and support bodies formed on the active TFT pixel arrays. Each of the active TFT pixel arrays includes a driving TFT and a switch TFT. The driving TFT has a gate insulation layer that has a thickness greater than a thickness of a gate insulation layer of the switch TFT. Through thickening the gate insulation layer of the driving TFT, the gate capacitance of the driving TFT can be reduced and the sub-threshold swing of the driving TFT is increased to realize well definition of grey levels.

Abstract: A ridged waveguide slot array includes a waveguide slot body having one or more walls that define a longitudinal axis of the waveguide slot body. The waveguide slot body includes a narrowed waveguide section having a plurality of slots disposed thereon which extend along the longitudinal axis, the waveguide slot body further characterized by a longitudinal center line. The waveguide slot body defines a waveguide aperture having a major dimension and a minor dimension, wherein the major dimension of the waveguide aperture is less than one-half wavelength of a signal intended for propagation therein. Each slot of the plurality of slots is characterized by a slot area, a slot offset distance that extends from the center of the slot to the longitudinal center line, and a slot-to-slot separation distance extending from the center of the slot to the center of an adjacent slot.

Abstract: A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED structures are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED structures. Each of the LED structures includes a first electrode and a second electrode. Light emitted from at least one of the LED structures passes through the transparent substrate and emerges from the second main surface. An illumination device includes the semiconductor light emitting element and a supporting base. The semiconductor light emitting element is disposed on the supporting base, and an angle is formed between the semiconductor light emitting element and the supporting base.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.

Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of light-blocking structures is disposed over the second side of the substrate. A passivation layer is coated on top surfaces and sidewalls of each of the light-blocking structures. A plurality of spacers is disposed on portions of the passivation layer coated on the sidewalls of the light-blocking structures.

Abstract: In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature.

Abstract: Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises five lens elements positioned sequentially from an object side to an image side. Through controlling the convex or concave shape of the surfaces and/or the refracting power of the lens elements and designing an equation, the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened.

Abstract: A graphene screening and separation method comprises the following steps. At least one pair of electrodes and an energy barrier layer is provided, wherein the pair of electrodes is a first electrode and a second electrode, and the energy barrier layer is formed on the first electrode. The pair of electrodes and the energy barrier layer are covered with a graphene suspension. When a graphene sheet in the graphene suspension materially couples the second electrode and the energy barrier layer and is located above the first electrode, a bias voltage between the first electrode and the second electrode of the pair of electrodes is changed and a corresponding tunneling current is measured. Screening and separation are performed by using differential conductance (i.e., the derivative of the tunneling current with respect to the bias voltage) of different layers of graphene.

Abstract: A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a dielectric material layer, a second conductive wiring layer, a second conductive pillar layer, and a first molding compound layer. The first conductive wiring layer has a first surface and a second surface opposite to the first surface. The first conductive pillar layer is disposed on the first surface of the first conductive wiring layer, wherein the first conductive wiring layer and the first conductive pillar layer are disposed inside the dielectric material layer. The second conductive wiring layer is disposed on the first conductive pillar layer and the dielectric material layer. The second conductive pillar layer is disposed on the second conductive wiring layer, wherein the second conductive wiring layer and the second conductive pillar layer are disposed inside the first molding compound layer.

Abstract: A sealed mat system discharge of a fluid or a solid material comprises interconnected channels, seals, and a composite panel structure.

Abstract: The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.

Abstract: A portable device capable of controlling output characteristics of an adaptor used for charging a battery of the portable device includes a sensing circuit and a controlling circuit. The sensing circuit senses a condition of the battery. The controlling circuit controls the adaptor to adjust its output characteristics based on the condition of the battery.

Abstract: A method of fabricating a package structure is provided, including forming a plurality of conductive pillars on a conductive layer, forming an insulating layer on the conductive layer and the conductive pillars, removing a portion of the conductive layer to allow the remaining portion of the conductive layer to serve as a wiring layer, disposing at least one electronic component on the wiring layer, and forming on the wiring layer and insulation layer an encapsulating layer to encapsulate the electronic component. Therefore, as there is already a wiring layer the wiring layer is capable of being integrated with the electronic component for allowing the conductive pillars to be bonded with solder balls to thereby shorten the signal transmission path. The present invention further provides a package structure thus fabricated.

Abstract: A method of fabricating an interposer substrate is provided, including: providing a carrier having a first wiring layer and a plurality of conductive pillars disposed on the first wiring layer; forming a first insulating layer on the carrier, with the first conductive pillars being exposed from the first insulating layer; forming on the first conductive pillars a second wiring layer that is electrically connected to the first conductive pillars; forming a plurality of second conductive pillars on the second wiring layer; forming on the first insulating layer a second insulating layer that covers the second wiring layer and the second conductive pillars, with terminal surfaces of the second conductive pillars being exposed from the second insulating layer; and removing the carrier. The first conductive pillars have terminal surfaces in geometric shapes, except for a circle. Therefore, the interposer substrate can have a layout on demands, and can be designed at a designer's will.

Abstract: A method of selectively transferring semiconductor devices comprises the steps of providing a substrate having a first surface and a second surface; providing a plurality of semiconductor epitaxial stacks on the first surface, wherein each of the plurality of semiconductor epitaxial stacks comprises a first semiconductor epitaxial stack and a second semiconductor epitaxial stack, and the first semiconductor epitaxial stack is apart from the second semiconductor epitaxial stack, and wherein a adhesion between the first semiconductor epitaxial stack and the substrate is different from a adhesion between the second semiconductor epitaxial stack and the substrate; and selectively separating the first semiconductor epitaxial stack or the second semiconductor epitaxial stack from the substrate.