Abstract: Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed. In some embodiments, concurrent operations occur among different banks of memory. In other embodiments, concurrent operations occur among different blocks of memory, where each block comprises two or more banks of memory. The embodiments substantially reduce the timing overhead for weight writing and verifying operations in analog neural memory systems.

Abstract: A delivery device for transtendinous implantation of a toggle-type suture anchor into bone is disclosed. The device includes a proximal housing having an outer tubular shaft extending distally with a lumen therethrough. An anchor delivery tube extends through the lumen of the outer tubular shaft having a proximal end affixed to the proximal housing. The anchor delivery tube includes a nub portion that is used to insert through the tendon and partly into bone to maintain registration with a bone hole into which an anchor is placed. A bone punch assembly extends through the lumen of the anchor delivery tube and the nub portion with a pointed distal end. When the bone punch is fully inserted, the pointed distal end extends a distance distal of the distal end of the nub portion.

Abstract: An assembly and method are provided for incorporation into suture anchor designs to facilitate the locking of a slidable working suture after it has been tensioned. The assembly can be utilized on multiple anchors in a pre-strung chain on a single working suture to create continuous, individually tensioned suture bridges between anchors in series, without knot tying. Further, the bridges are independently locked with selected tension for the particular application. An anchor body having at least one suture receiving passage therethrough is threaded with a working suture wherein the working suture flosses through the passage when tension is applied to the working suture. A locking cord extends through a second passage through the anchor body, the locking cord having a collapsible loop extending out the second passage and encircling a portion of the working suture, wherein collapsing the loop locks the working suture after tensioning.

Abstract: A method and apparatus are provided for transtendinous implantation of a toggle-type bone anchor. Measured from the top surface of the tendon, the entire bone anchor is inserted to a depth of greater than or equal to 20 mm. during a rotator cuff repair on the humeral head. The anchor is pushed by the same bone punch that formed the initial hole to assure proper depth of placement. Further, the apparatus includes a nub portion that, in use, protrudes into the bone hole formed by the bone punch and maintains registration with the bone hole when the bone punch is retracted. An angled distal end on the anchor initiates toggling during insertion into the bone and at least one proximal projecting fin prevents the anchor from backing out of the bone hole while facilitating further rotation of the anchor when a suture is pulled to complete toggling.

Abstract: In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.

Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

Abstract: In one example, a method comprises determining a program resolution current value; and setting levels for a programming operation of a plurality of non-volatile memory cells in a neural network array such that a delta current between levels of each pair of adjacent cells in the plurality is a multiple of the program resolution current value.

Abstract: A method for partially publishing edits to a document is described. A first document including a first cell and a second cell is displayed on first user account on a first computing device and on a second user account. A second document including a linked version of the first cell and a linked version of the second cell is displayed. An edit of the first cell is received from the first user account and an edit of the second cell is received. In response to receiving an indication from the first user account that the edit of the first cell is to be published, the edit of the first cell is made to the linked version of the first cell, while the linked version of the second cell is unchanged so that the content of the linked version of the second cell no longer matches that of the second cell.

Abstract: A portable towing system for motorcycles or similar vehicles, such as trikes, features a frame that can be lowered to ground level for easy loading by pushing or riding the vehicle onto the frame. The system can be assembled, raised, lowered, and disassembled by a single person. Raising and lowering are achieved through a mechanism connected to the wheel assemblies. The system includes a towable cargo container with a walled container, a top that opens and closes, and left and right side openings in the rear sidewall. Left and right wheel assemblies with elongated tubes are insertable into these openings, oriented orthogonally to the wheel axes. A receiver for a vehicle tow bar allows the cargo container to be towed when connected to a vehicle.

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: A toggle-type suture anchor for transtendinous implantation in bone to secure soft tissue thereto during repair of a tear, especially a rotator cuff repair. The anchor can include an elongate body with side surfaces defining a maximum diameter of the body. The body can also include proximal, middle and distal bores extending from the top surface to the bottom surface, each bore located at spaced intervals along the elongate body with a single suture passing into the proximal bore top surface and out the bottom surface, then back up through the distal bore bottom surface out the top surface leaving a length of suture extending past the middle bore bottom surface. To assure toggling in transtendinous delivery into bone, the elongate body can include a pair of fins extending both proximally and radially outward from the elongate body to prevent back out once placed in a bone hole.

Abstract: A toggle-type suture anchor that incorporates individual suture tensioning and locking without knot tying. The anchor includes an elongate toggle body having a working suture pre-threaded into a first passage and back up and out a second passage with a length running longitudinally adjacent the side of the anchor. A locking suture loop is pre-threaded into a third passage between the first and second passage and includes a collapsible loop that encircles a portion of the length of suture running longitudinally adjacent the side of the anchor. With the loop open, the working suture can slide through the anchor, however, when the loop is closed the working suture is locked in position to retain tension on the working suture. The anchor can be utilized in a pre-strung connected array of anchors.

Abstract: In one example, a circuit for comparing current drawn by a selected memory cell for a vector-matrix-multiplier with current drawn by a reference matrix comprises a first circuit comprising a first PMOS transistor coupled to a first NMOS transistor coupled to the selected memory cell; and a second circuit comprising a second PMOS transistor coupled to a second NMOS transistor coupled to the reference matrix; wherein a node between the second PMOS transistor and the second NMOS transistor outputs a current indicative of a value stored in the selected memory cell.

Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m?2u, n?2v, and p?2t.

Abstract: In one example disclosed herein, a system comprises an analog computation-in-memory engine to perform operations in a first layer in a neural network and a digital computation-in-memory engine to perform operations in a second layer different than the first layer in the neural network. The system optionally comprises a dynamic weight engine to perform operations in a third layer different than the first layer and the second layer in the neural network.

Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

Abstract: Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.