Abstract: This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on the P well. A self-aligned implantation is performed to form N-type diode diffusion within the light-sensing region. An oblique ion implantation process is then performed to form N-type pocket diffusion directly under the gate electrode. Spacers are formed on sidewalls of the gate electrode. A surface P+ pinning diffusion region is then formed in the diode diffusion region.

Abstract: An organic electroluminescent panel having a silver alloy is disclosed, which has a substrate; a plurality of the first electrodes; a plurality of the second electrodes; a plurality of conducting lines containing a silver alloy; a plurality of isolating walls; and a plurality of organic electroluminescent media. The first electrodes are arranged in parallel on the substrate. The organic electroluminescent media are disposed on the first electrodes. The second electrodes are disposed on the organic electroluminescent media. The conducting lines containing the silver alloy connect to the first electrodes or the second electrodes. The silver alloy contained in the conducting lines has 80 to 99.8 mol % of silver; 0.1 to 10 mol % of copper; and 0.1 to 10 mol % of at least one transition metal selected from the group consisting of palladium (Pd), magnesium (Mg), gold (Au), platinum (Pt), and the combinations thereof.

Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

Abstract: A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2?t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)?GD2 for the second copper layer.

Abstract: The present invention discloses a DC/AC converter in the backlight power supply system using cold cathode fluorescent lamp (CCFL). The DC/AC converter comprises a front end DC/DC converter, a full-bridge or half bridge inverter, and a piezoelectric transformer. Even with a wide range of input voltages, the front end DC/DC converter produces a predetermined DC voltage or a DC voltage with a predetermined small range and the cascaded inverter operates with a switching frequency close to the resonant frequency of the piezoelectric transformer, which helps the backlight power supply system achieve high efficiency.

Abstract: A pre-treatment method for physical vapor deposition of a metal layer is provided. A substrate is first provided and then a dry cleaning process is performed to the substrate using a chemical etching process, in which the chemical etching process causes a reaction to the oxide. Thereafter, an annealing process is performed, followed by a cooling process. Due to the treatment prior to depositing of the metal layer, subsequent metal layers from ill effects are prevented.

Abstract: Methods and apparatus are disclosed for converting DC power to AC and for driving multiple discharge lamps and, more particularly, Cold Cathode Fluorescent Lamps (CCFLs), External Electrode Fluorescent Lamps (EEFLs), and Flat Fluorescent Lamps (FFLs). Disclosed methods, among other advantages, allow accurate current sharing among the lamps, minimization of the total number of power switches, and, in general, simplification of the complexity of the control system.

Abstract: The present invention discloses a method for arranging heap memory. The method is to utilize a memory-management function library positioned in the run-time library for use during run time and designate two sets of heap memory, wherein one set of heap memory is arranged in a dynamic random access memory (DRAM) whereas the other set of heap memory is arranged in a static random access memory (SRAM). In addition, an application program interface is added to indicate a start point and size of the heap memory. Furthermore, a parameter is added to the application program interface for calling one set of heap memory when allocating memory. By doing so, the programmer can select a position to allocate the memory according to the executable content. Therefore, when the processor is executing calculation or accessing memory, the efficiency can be well enhanced.

Abstract: A novel light mixing plate and a direct backlight module using the light mixing plate are provided herein. The light mixing plate has a first surface and a second surface, in which a number of indented grooves are configured along the first surface to accommodate the LED light sources. The lights from the LEDs enter the light mixing plate via the side walls of the grooves and propagate an extended distance inside the light mixing plate so that they are fully mixed with each other into a uniform planar white light when leaving the light mixing plate via the second surface.

Abstract: A semiconductor device with electroless plating metal connecting layer and a method for fabricating the same are proposed. A supporting board with at least one cavity is provided. At least one semiconductor chip with a plurality of copper electrode pads is received in the cavity and an insulating protecting layer is formed on the semiconductor chip. A plurality of holes is formed in the insulating protecting layer to expose the copper electrode pads. An electroless plating metal connecting layer is formed on the copper electrode pads by electroless plating. Therefore, the electrically connecting process of the semiconductor chip is simplified and easily practiced, and the fabrication cost is reduced.

Abstract: Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.

Abstract: Compounds are provided that act as potent antagonists of the CCR1 receptor, and have in vivo anti-inflammatory activity. The compounds are generally monocyclic and bicyclic compounds and are useful in pharmaceutical compositions, methods for the treatment of CCR1-mediated diseases, and as controls in assays for the identification of competitive CCR1 antagonists.

Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

Abstract: A method for forming a metal silicide over a substrate is provided. The method comprises steps of performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system. Then, a vacuum system of the first tool system is broken. The substrate is transferred from the first tool system into a second tool system. A metal silicide layer is formed over the substrate in the second tool system.

Abstract: An antenna apparatus has a substrate, a plurality of meandered conductive strips and a feeding conductive strip disposed on the substrate. The meandered conductive strips have different sizes, and are spaced at intervals and arranged in parallel according to their sizes in order. The feeding conductive strip is electrically connected to the meandered conductive strips. Therefore, a radiating structure having multiple meandered conductive strips can generate electromagnetic mutual coupling, thus obtaining the resonance of multiple and wide-frequency bands.

Abstract: A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.

Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Abstract: A data storage virtualization subsystem (SVS) for providing storage to a host entity is disclosed. The SVS comprises a storage virtualization controller for connecting to the host entity, at least one physical storage device (PSD) pool, and at least one PSD is designated to be a pool spare PSD to the at least one PSD pool. The at least one PSD pool comprises at least one PSD to store user data or associated redundant information and is given a pool ID for identifying the PSD pool.

Abstract: A data storage unit access authorization table automatic rebuilding method and system is proposed, which is designed for use with a data storage unit for providing an access authorization table automatic rebuilding capability for the data storage unit, and which is characterized by the capability of partitioning a special area from the storage space of the data storage unit for the storage of access authorization data, such that in the event that the data storage unit is removed from a first computer platform and reinstalled on a second one, it allows the second computer platform to automatically rebuild an access authorization table that is identical with the original access authorization table on the first computer platform by retrieving the access authorization data stored in the data storage unit.

Abstract: A shared-IRQ user-defined interrupt signal handling method and system is proposed, which is designed for use with a computer platform to allow a group of peripheral devices connected to an interrupt-configurable peripheral interface to share system interrupt lines IRQ with another group of peripheral devices connected to an interrupt nonconfigurable peripheral interface; which is characterized by the provision of an interrupt configuration table for defining a virtual device for the interrupt-configurable peripheral interface as well as each specific system interrupt line that is shared by the two groups of peripheral devices. This feature allows system interrupt lines IRQ to be shared by the two different groups of peripheral devices, and also allows the implementation to be easier to carried out than prior art without involving complex and difficult BIOS coding.